INSTRUCTION SET REFERENCE, N-Z

NEG—Two's Complement Negation

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En Mode

Leg Mode

F6 /3

NEG r/m8

M Valid

Valid

Two's complement negate r/m8.

REX + F6 /3

NEG r/m8*

M Valid

N.E.

Two's complement negate r/m8.

F7 /3

NEG r/m16

M Valid

Valid

Two's complement negate r/m16.

F7 /3

NEG r/m32

M Valid

Valid

Two's complement negate r/m32.

REX.W + F7 /3

NEG r/m64

M Valid

N.E.

Two's complement negate r/m64.

NOTES:

* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:r/m (r, w)

Description

Replaces the value of operand (the destination operand) with its two's complement. (This operation is equivalent to

subtracting the operand from 0.) The destination operand is located in a general-purpose register or a memory

location.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.

In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits

access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See

the summary chart at the beginning of this section for encoding data and limits.

Operation

IF DEST = 0

THEN CF ← 0;

ELSE CF ← 1;

FI;

DEST ← [- (DEST)]

Flags Affected

The CF flag set to 0 if the source operand is 0; otherwise it is set to 1. The OF, SF, ZF, AF, and PF flags are set

according to the result.

Protected Mode Exceptions

#GP(0)

If the destination is located in a non-writable segment.

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

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Vol. 2B

NEG—Two's Complement Negation

INSTRUCTION SET REFERENCE, N-Z

Real-Address Mode Exceptions

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

If a memory operand effective address is outside the SS segment limit.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#GP(0)

If the memory address is in a non-canonical form.

#PF(fault-code)

For a page fault.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

NEG—Two's Complement Negation

Vol. 2B

4-7

INSTRUCTION SET REFERENCE, N-Z

NOP—No Operation

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En Mode

Leg Mode

NOP

NP Valid

Valid

One byte no-operation instruction.

0F 1F /0

NOP r/m16

M Valid

Valid

Multi-byte no-operation instruction.

0F 1F /0

NOP r/m32

M Valid

Valid

Multi-byte no-operation instruction.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:r/m (r)

Description

This instruction performs no operation. It is a one-byte or multi-byte NOP that takes up space in the instruction

stream but does not impact machine context, except for the EIP register.

The multi-byte form of NOP is available on processors with model encoding:

• CPUID.01H.EAX[Bytes 11:8] = 0110B or 1111B

The multi-byte NOP instruction does not alter the content of a register and will not issue a memory operation. The

instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

The one-byte NOP instruction is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.

The multi-byte NOP instruction performs no operation on supported processors and generates undefined opcode

exception on processors that do not support the multi-byte NOP instruction.

The memory operand form of the instruction allows software to create a byte sequence of “no operation” as one

instruction. For situations where multiple-byte NOPs are needed, the recommended operations (32-bit mode and

64-bit mode) are:

Table 4-9. Recommended Multi-Byte Sequence of NOP Instruction

Length

Assembly

Byte Sequence

2 bytes

66 NOP

66 90H

3 bytes

NOP DWORD ptr [EAX]

0F 1F 00H

4 bytes

NOP DWORD ptr [EAX + 00H]

0F 1F 40 00H

5 bytes

NOP DWORD ptr [EAX + EAX*1 + 00H]

0F 1F 44 00 00H

6 bytes

66 NOP DWORD ptr [EAX + EAX*1 + 00H]

66 0F 1F 44 00 00H

7 bytes

NOP DWORD ptr [EAX + 00000000H]

0F 1F 80 00 00 00 00H

8 bytes

NOP DWORD ptr [EAX + EAX*1 + 00000000H]

0F 1F 84 00 00 00 00 00H

9 bytes

66 NOP DWORD ptr [EAX + EAX*1 + 00000000H]

66 0F 1F 84 00 00 00 00 00H

Flags Affected

None.

Exceptions (All Operating Modes)

#UD

If the LOCK prefix is used.

4-8

Vol. 2B

NOP—No Operation

INSTRUCTION SET REFERENCE, N-Z

NOT—One's Complement Negation

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En Mode

Leg Mode

F6 /2

NOT r/m8

M Valid

Valid

Reverse each bit of r/m8.

REX + F6 /2

NOT r/m8*

M Valid

N.E.

Reverse each bit of r/m8.

F7 /2

NOT r/m16

M Valid

Valid

Reverse each bit of r/m16.

F7 /2

NOT r/m32

M Valid

Valid

Reverse each bit of r/m32.

REX.W + F7 /2

NOT r/m64

M Valid

N.E.

Reverse each bit of r/m64.

NOTES:

* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:r/m (r, w)

Description

Performs a bitwise NOT operation (each 1 is set to 0, and each 0 is set to 1) on the destination operand and stores

the result in the destination operand location. The destination operand can be a register or a memory location.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.

In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits

access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See

the summary chart at the beginning of this section for encoding data and limits.

Operation

DEST ← NOT DEST;

Flags Affected

None.

Protected Mode Exceptions

#GP(0)

If the destination operand points to a non-writable segment.

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

If a memory operand effective address is outside the SS segment limit.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

NOT—One's Complement Negation

Vol. 2B

4-9

INSTRUCTION SET REFERENCE, N-Z

Virtual-8086 Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#GP(0)

If the memory address is in a non-canonical form.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

4-10

Vol. 2B

NOT—One's Complement Negation

INSTRUCTION SET REFERENCE, N-Z

OR—Logical Inclusive OR

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

0C ib

OR AL, imm8

Valid

AL OR imm8.

0D iw

OR AX, imm16

Valid

AX OR imm16.

0D id

OR EAX, imm32

Valid

EAX OR imm32.

REX.W + 0D id

OR RAX, imm32

Valid

N.E.

RAX OR imm32 (sign-extended).

80 /1 ib

OR r/m8, imm8

Valid

r/m8 OR imm8.

REX + 80 /1 ib

OR r/m8*, imm8

Valid

N.E.

r/m8 OR imm8.

81 /1 iw

OR r/m16, imm16

Valid

r/m16 OR imm16.

81 /1 id

OR r/m32, imm32

Valid

r/m32 OR imm32.

REX.W + 81 /1 id

OR r/m64, imm32

Valid

N.E.

r/m64 OR imm32 (sign-extended).

83 /1 ib

OR r/m16, imm8

Valid

r/m16 OR imm8 (sign-extended).

83 /1 ib

OR r/m32, imm8

Valid

r/m32 OR imm8 (sign-extended).

REX.W + 83 /1 ib

OR r/m64, imm8

Valid

N.E.

r/m64 OR imm8 (sign-extended).

08 /r

OR r/m8, r8

Valid

r/m8 OR r8.

REX + 08 /r

OR r/m8*, r8*

Valid

N.E.

r/m8 OR r8.

09 /r

OR r/m16, r16

Valid

r/m16 OR r16.

09 /r

OR r/m32, r32

Valid

r/m32 OR r32.

REX.W + 09 /r

OR r/m64, r64

Valid

N.E.

r/m64 OR r64.

0A /r

OR r8, r/m8

Valid

r8 OR r/m8.

REX + 0A /r

OR r8*, r/m8*

Valid

N.E.

r8 OR r/m8.

0B /r

OR r16, r/m16

Valid

r16 OR r/m16.

0B /r

OR r32, r/m32

Valid

r32 OR r/m32.

REX.W + 0B /r

OR r64, r/m64

Valid

N.E.

r64 OR r/m64.

NOTES:

* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

AL/AX/EAX/RAX

imm8/16/32

ModRM:r/m (r, w)

imm8/16/32

ModRM:r/m (r, w)

ModRM:reg (r)

ModRM:reg (r, w)

ModRM:r/m (r)

Description

Performs a bitwise inclusive OR operation between the destination (first) and source (second) operands and stores

the result in the destination operand location. The source operand can be an immediate, a register, or a memory

location; the destination operand can be a register or a memory location. (However, two memory operands cannot

be used in one instruction.) Each bit of the result of the OR instruction is set to 0 if both corresponding bits of the

first and second operands are 0; otherwise, each bit is set to 1.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.

OR—Logical Inclusive OR

Vol. 2B

4-11

INSTRUCTION SET REFERENCE, N-Z

In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits

access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See

the summary chart at the beginning of this section for encoding data and limits.

Operation

DEST ← DEST OR SRC;

Flags Affected

The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is

undefined.

Protected Mode Exceptions

#GP(0)

If the destination operand points to a non-writable segment.

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

If a memory operand effective address is outside the SS segment limit.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#GP(0)

If the memory address is in a non-canonical form.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

4-12

Vol. 2B

OR—Logical Inclusive OR

INSTRUCTION SET REFERENCE, N-Z

ORPD—Bitwise Logical OR of Double-Precision Floating-Point Values

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

66 0F 56 /r

RM V/V

SSE2

Bitwise OR of xmm2/m128 and xmm1.

ORPD xmm1, xmm2/m128

VEX.NDS.128.66.0F.WIG 56 /r

RVM V/V

AVX

Return the bitwise logical OR of packed

VORPD xmm1,xmm2, xmm3/m128

double-precision floating-point values in

xmm2 and xmm3/mem.

VEX.NDS.256.66.0F.WIG 56 /r

RVM V/V

AVX

Return the bitwise logical OR of packed

double-precision floating-point values in

VORPD ymm1, ymm2, ymm3/m256

ymm2 and ymm3/mem.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

Description

Performs a bitwise logical OR of the two or four packed double-precision floating-point values from the first source

operand and the second source operand, and stores the result in the destination operand

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers

(XMM8-XMM15).

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding

YMM register destination are unmodified.

VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination

operand is an XMM register. The upper bits (VLMAX-1:128) of the destination YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

Note: If VORPD is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause

an #UD exception.

Operation

ORPD (128-bit Legacy SSE version)

DEST[63:0]  DEST[63:0] BITWISE OR SRC[63:0]

DEST[127:64]  DEST[127:64] BITWISE OR SRC[127:64]

DEST[VLMAX-1:128] (Unmodified)

VORPD (VEX.128 encoded version)

DEST[63:0]  SRC1[63:0] BITWISE OR SRC2[63:0]

DEST[127:64]  SRC1[127:64] BITWISE OR SRC2[127:64]

DEST[VLMAX-1:128]  0

VORPD (VEX.256 encoded version)

DEST[63:0]  SRC1[63:0] BITWISE OR SRC2[63:0]

DEST[127:64]  SRC1[127:64] BITWISE OR SRC2[127:64]

DEST[191:128]  SRC1[191:128] BITWISE OR SRC2[191:128]

DEST[255:192]  SRC1[255:192] BITWISE OR SRC2[255:192]

ORPD—Bitwise Logical OR of Double-Precision Floating-Point Values

Vol. 2B

4-13

INSTRUCTION SET REFERENCE, N-Z

ORPS—Bitwise Logical OR of Single-Precision Floating-Point Values

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

0F 56 /r

RM V/V

SSE

Bitwise OR of xmm1 and xmm2/m128.

ORPS xmm1, xmm2/m128

VEX.NDS.128.0F.WIG 56 /r

RVM V/V

AVX

Return the bitwise logical OR of packed single-

precision floating-point values in xmm2 and

VORPS xmm1, xmm2, xmm3/m128

xmm3/mem.

VEX.NDS.256.0F.WIG 56 /r

RVM V/V

AVX

Return the bitwise logical OR of packed single-

precision floating-point values in ymm2 and

VORPS ymm1, ymm2, ymm3/m256

ymm3/mem.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

Description

Performs a bitwise logical OR of the four or eight packed single-precision floating-point values from the first source

operand and the second source operand, and stores the result in the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers

(XMM8-XMM15).

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding

YMM register destination are unmodified.

VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination

operand is an XMM register. The upper bits (VLMAX-1:128) of the destination YMM register destination are zeroed.

VEX.256 Encoded version: The first source operand is a YMM register. The second source operand can be a YMM

Note: If VORPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause

an #UD exception.

Operation

ORPS (128-bit Legacy SSE version)

DEST[31:0]  SRC1[31:0] BITWISE OR SRC2[31:0]

DEST[63:32]  SRC1[63:32] BITWISE OR SRC2[63:32]

DEST[95:64]  SRC1[95:64] BITWISE OR SRC2[95:64]

DEST[127:96]  SRC1[127:96] BITWISE OR SRC2[127:96]

DEST[VLMAX-1:128] (Unmodified)

VORPS (VEX.128 encoded version)

DEST[31:0]  SRC1[31:0] BITWISE OR SRC2[31:0]

DEST[63:32]  SRC1[63:32] BITWISE OR SRC2[63:32]

DEST[95:64]  SRC1[95:64] BITWISE OR SRC2[95:64]

DEST[127:96]  SRC1[127:96] BITWISE OR SRC2[127:96]

DEST[VLMAX-1:128]  0

ORPS—Bitwise Logical OR of Single-Precision Floating-Point Values

Vol. 2B

4-15

INSTRUCTION SET REFERENCE, N-Z

OUT—Output to Port

Opcode*

Instruction

Op/

64-Bit

Compat/ Description

En Mode

Leg Mode

E6 ib

OUT imm8, AL

Valid

Output byte in AL to I/O port address imm8.

E7 ib

OUT imm8, AX

Valid

Output word in AX to I/O port address imm8.

E7 ib

OUT imm8, EAX

Valid

Output doubleword in EAX to I/O port address

imm8.

OUT DX, AL

NP Valid

Valid

Output byte in AL to I/O port address in DX.

OUT DX, AX

NP Valid

Valid

Output word in AX to I/O port address in DX.

OUT DX, EAX

NP Valid

Valid

Output doubleword in EAX to I/O port address

in DX.

NOTES:

* See IA-32 Architecture Compatibility section below.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

imm8

Description

Copies the value from the second operand (source operand) to the I/O port specified with the destination operand

(first operand). The source operand can be register AL, AX, or EAX, depending on the size of the port being

accessed (8, 16, or 32 bits, respectively); the destination operand can be a byte-immediate or the DX register.

Using a byte immediate allows I/O port addresses 0 to 255 to be accessed; using the DX register as a source

operand allows I/O ports from 0 to 65,535 to be accessed.

The size of the I/O port being accessed is determined by the opcode for an 8-bit I/O port or by the operand-size

attribute of the instruction for a 16- or 32-bit I/O port.

At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits

of the port address will be 0.

This instruction is only useful for accessing I/O ports located in the processor’s I/O address space. See Chapter 16,

“Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more infor-

mation on accessing I/O ports in the I/O address space.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

IA-32 Architecture Compatibility

After executing an OUT instruction, the Pentium^® processor ensures that the EWBE# pin has been sampled active

before it begins to execute the next instruction. (Note that the instruction can be prefetched if EWBE# is not active,

but it will not be executed until the EWBE# pin is sampled active.) Only the Pentium processor family has the

EWBE# pin.

OUT—Output to Port

Vol. 2B

4-17

INSTRUCTION SET REFERENCE, N-Z

Operation

IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))

THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)

IF (Any I/O Permission Bit for I/O port being accessed = 1)

THEN (* I/O operation is not allowed *)

#GP(0);

ELSE ( * I/O operation is allowed *)

DEST ← SRC; (* Writes to selected I/O port *)

FI;

ELSE (Real Mode or Protected Mode with CPL ≤ IOPL *)

DEST ← SRC; (* Writes to selected I/O port *)

FI;

Flags Affected

None.

Protected Mode Exceptions

#GP(0)

If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the

corresponding I/O permission bits in TSS for the I/O port being accessed is 1.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

#UD

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0)

If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.

#PF(fault-code)

If a page fault occurs.

#UD

If the LOCK prefix is used.

Compatibility Mode Exceptions

Same as protected mode exceptions.

64-Bit Mode Exceptions

Same as protected mode exceptions.

4-18

Vol. 2B

OUT—Output to Port

INSTRUCTION SET REFERENCE, N-Z

OUTS/OUTSB/OUTSW/OUTSD—Output String to Port

Opcode*

Instruction

Op/

64-Bit

Compat/ Description

En Mode

Leg Mode

OUTS DX, m8

NP Valid

Valid

Output byte from memory location specified

in DS:(E)SI or RSI to I/O port specified in DX**.

OUTS DX, m16

NP Valid

Valid

Output word from memory location specified

in DS:(E)SI or RSI to I/O port specified in DX**.

OUTS DX, m32

NP Valid

Valid

Output doubleword from memory location

specified in DS:(E)SI or RSI to I/O port specified

in DX**.

OUTSB

NP Valid

Valid

Output byte from memory location specified

in DS:(E)SI or RSI to I/O port specified in DX**.

OUTSW

NP Valid

Valid

Output word from memory location specified

in DS:(E)SI or RSI to I/O port specified in DX**.

OUTSD

NP Valid

Valid

Output doubleword from memory location

specified in DS:(E)SI or RSI to I/O port specified

in DX**.

NOTES:

* See IA-32 Architecture Compatibility section below.

** In 64-bit mode, only 64-bit (RSI) and 32-bit (ESI) address sizes are supported. In non-64-bit mode, only 32-bit (ESI) and 16-bit (SI)

address sizes are supported.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

Description

Copies data from the source operand (second operand) to the I/O port specified with the destination operand (first

operand). The source operand is a memory location, the address of which is read from either the DS:SI, DS:ESI or

the RSI registers (depending on the address-size attribute of the instruction, 16, 32 or 64, respectively). (The DS

segment may be overridden with a segment override prefix.) The destination operand is an I/O port address (from

0 to 65,535) that is read from the DX register. The size of the I/O port being accessed (that is, the size of the source

and destination operands) is determined by the opcode for an 8-bit I/O port or by the operand-size attribute of the

instruction for a 16- or 32-bit I/O port.

At the assembly-code level, two forms of this instruction are allowed: the “explicit-operands” form and the “no-

operands” form. The explicit-operands form (specified with the OUTS mnemonic) allows the source and destination

operands to be specified explicitly. Here, the source operand should be a symbol that indicates the size of the I/O

port and the source address, and the destination operand must be DX. This explicit-operands form is provided to

allow documentation; however, note that the documentation provided by this form can be misleading. That is, the

source operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it

does not have to specify the correct location. The location is always specified by the DS:(E)SI or RSI registers,

which must be loaded correctly before the OUTS instruction is executed.

The no-operands form provides “short forms” of the byte, word, and doubleword versions of the OUTS instructions.

Here also DS:(E)SI is assumed to be the source operand and DX is assumed to be the destination operand. The size

of the I/O port is specified with the choice of mnemonic: OUTSB (byte), OUTSW (word), or OUTSD (doubleword).

After the byte, word, or doubleword is transferred from the memory location to the I/O port, the SI/ESI/RSI

(If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the SI/ESI/RSI register is decremented.)

The SI/ESI/RSI register is incremented or decremented by 1 for byte operations, by 2 for word operations, and by

4 for doubleword operations.

OUTS/OUTSB/OUTSW/OUTSD—Output String to Port

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INSTRUCTION SET REFERENCE, N-Z

The OUTS, OUTSB, OUTSW, and OUTSD instructions can be preceded by the REP prefix for block input of ECX bytes,

words, or doublewords. See “REP/REPE/REPZ /REPNE/REPNZ—Repeat String Operation Prefix” in this chapter for a

description of the REP prefix. This instruction is only useful for accessing I/O ports located in the processor’s I/O

address space. See Chapter 16, “Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 1, for more information on accessing I/O ports in the I/O address space.

In 64-bit mode, the default operand size is 32 bits; operand size is not promoted by the use of REX.W. In 64-bit

mode, the default address size is 64 bits, and 64-bit address is specified using RSI by default. 32-bit address using

ESI is support using the prefix 67H, but 16-bit address is not supported in 64-bit mode.

IA-32 Architecture Compatibility

After executing an OUTS, OUTSB, OUTSW, or OUTSD instruction, the Pentium processor ensures that the EWBE#

pin has been sampled active before it begins to execute the next instruction. (Note that the instruction can be

prefetched if EWBE# is not active, but it will not be executed until the EWBE# pin is sampled active.) Only the

Pentium processor family has the EWBE# pin.

For the Pentium 4, Intel^® Xeon^®, and P6 processor family, upon execution of an OUTS, OUTSB, OUTSW, or OUTSD

instruction, the processor will not execute the next instruction until the data phase of the transaction is complete.

Operation

IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))

THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)

IF (Any I/O Permission Bit for I/O port being accessed = 1)

THEN (* I/O operation is not allowed *)

#GP(0);

ELSE (* I/O operation is allowed *)

DEST ← SRC; (* Writes to I/O port *)

FI;

ELSE (Real Mode or Protected Mode or 64-Bit Mode with CPL ≤ IOPL *)

DEST ← SRC; (* Writes to I/O port *)

FI;

Byte transfer:

IF 64-bit mode

Then

IF 64-Bit Address Size

THEN

IF DF = 0

THEN RSI ← RSI RSI + 1;

ELSE RSI ← RSI or - 1;

FI;

ELSE (* 32-Bit Address Size *)

IF DF = 0

THEN ESI ← ESI + 1;

ELSE

ESI ← ESI - 1;

FI;

ELSE

IF DF = 0

THEN

(E)SI ← (E)SI + 1;

ELSE (E)SI ← (E)SI - 1;

FI;

Word transfer:

IF 64-bit mode

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OUTS/OUTSB/OUTSW/OUTSD—Output String to Port

INSTRUCTION SET REFERENCE, N-Z

Then

IF 64-Bit Address Size

THEN

IF DF = 0

THEN RSI ← RSI RSI + 2;

ELSE RSI ← RSI or - 2;

FI;

ELSE (* 32-Bit Address Size *)

IF DF = 0

THEN ESI ← ESI + 2;

ELSE

ESI ← ESI - 2;

FI;

ELSE

IF DF = 0

THEN

(E)SI ← (E)SI + 2;

ELSE (E)SI ← (E)SI - 2;

FI;

Doubleword transfer:

IF 64-bit mode

Then

IF 64-Bit Address Size

THEN

IF DF = 0

THEN RSI ← RSI RSI + 4;

ELSE RSI ← RSI or - 4;

FI;

ELSE (* 32-Bit Address Size *)

IF DF = 0

THEN ESI ← ESI + 4;

ELSE

ESI ← ESI - 4;

FI;

ELSE

IF DF = 0

THEN

(E)SI ← (E)SI + 4;

ELSE (E)SI ← (E)SI - 4;

FI;

Flags Affected

None.

Protected Mode Exceptions

#GP(0)

If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the

corresponding I/O permission bits in TSS for the I/O port being accessed is 1.

If a memory operand effective address is outside the limit of the CS, DS, ES, FS, or GS

segment.

If the segment register contains a NULL segment selector.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

OUTS/OUTSB/OUTSW/OUTSD—Output String to Port

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INSTRUCTION SET REFERENCE, N-Z

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

If a memory operand effective address is outside the SS segment limit.

#UD

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0)

If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If the LOCK prefix is used.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#GP(0)

If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the

corresponding I/O permission bits in TSS for the I/O port being accessed is 1.

If the memory address is in a non-canonical form.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

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OUTS/OUTSB/OUTSW/OUTSD—Output String to Port

INSTRUCTION SET REFERENCE, N-Z

PABSB/PABSW/PABSD — Packed Absolute Value

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

0F 38 1C /r¹

V/V

SSSE3

Compute the absolute value of bytes in

PABSB mm1, mm2/m64

mm2/m64 and store UNSIGNED result in mm1.

66 0F 38 1C /r

V/V

SSSE3

Compute the absolute value of bytes in

xmm2/m128 and store UNSIGNED result in

PABSB xmm1, xmm2/m128

xmm1.

0F 38 1D /r¹

V/V

SSSE3

Compute the absolute value of 16-bit integers

in mm2/m64 and store UNSIGNED result in

PABSW mm1, mm2/m64

mm1.

66 0F 38 1D /r

V/V

SSSE3

Compute the absolute value of 16-bit integers

in xmm2/m128 and store UNSIGNED result in

PABSW xmm1, xmm2/m128

xmm1.

0F 38 1E /r¹

V/V

SSSE3

Compute the absolute value of 32-bit integers

in mm2/m64 and store UNSIGNED result in

PABSD mm1, mm2/m64

mm1.

66 0F 38 1E /r

V/V

SSSE3

Compute the absolute value of 32-bit integers

in xmm2/m128 and store UNSIGNED result in

PABSD xmm1, xmm2/m128

xmm1.

VEX.128.66.0F38.WIG 1C /r

V/V

AVX

Compute the absolute value of bytes in

xmm2/m128 and store UNSIGNED result in

VPABSB xmm1, xmm2/m128

xmm1.

VEX.128.66.0F38.WIG 1D /r

V/V

AVX

Compute the absolute value of 16- bit

integers in xmm2/m128 and store UNSIGNED

VPABSW xmm1, xmm2/m128

result in xmm1.

VEX.128.66.0F38.WIG 1E /r

V/V

AVX

Compute the absolute value of 32- bit

integers in xmm2/m128 and store UNSIGNED

VPABSD xmm1, xmm2/m128

result in xmm1.

VEX.256.66.0F38.WIG 1C /r

V/V

AVX2

Compute the absolute value of bytes in

VPABSB ymm1, ymm2/m256

ymm2/m256 and store UNSIGNED result in

ymm1.

VEX.256.66.0F38.WIG 1D /r

V/V

AVX2

Compute the absolute value of 16-bit integers

in ymm2/m256 and store UNSIGNED result in

VPABSW ymm1, ymm2/m256

ymm1.

VEX.256.66.0F38.WIG 1E /r

V/V

AVX2

Compute the absolute value of 32-bit integers

in ymm2/m256 and store UNSIGNED result in

VPABSD ymm1, ymm2/m256

ymm1.

NOTES:

1. See note in Section 2.4, “Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (w)

ModRM:r/m (r)

PABSB/PABSW/PABSD — Packed Absolute Value

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INSTRUCTION SET REFERENCE, N-Z

Description

(V)PABSB/W/D computes the absolute value of each data element of the source operand (the second operand) and

stores the UNSIGNED results in the destination operand (the first operand). (V)PABSB operates on signed bytes,

(V)PABSW operates on 16-bit words, and (V)PABSD operates on signed 32-bit integers. The source operand can be

an MMX register or a 64-bit memory location, or it can be an XMM register, a YMM register, a 128-bit memory loca-

tion, or a 256-bit memory location. The destination operand can be an MMX, an XMM or a YMM register. Both oper-

ands can be MMX registers or XMM registers. When the source operand is a 128-bit memory operand, the operand

must be aligned on a 16byte boundary or a general-protection exception (#GP) will be generated.

In 64-bit mode, use the REX prefix to access additional registers.

128-bit Legacy SSE version: The source operand can be an XMM register or a 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding

YMM register destination are unmodified.

VEX.128 encoded version: The source operand is an XMM register or 128-bit memory location. The destination

operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are

zeroed.

VEX.256 encoded version: The first source operand is a YMM register or a 256-bit memory location. The destination

operand is a YMM register.

Note: VEX.vvvv is reserved and must be 1111b, VEX.L must be 0; otherwise instructions will #UD.

Operation

PABSB (with 64 bit operands)

Unsigned DEST[7:0] ← ABS(SRC[7:0])

Repeat operation for 2nd through 7th bytes

Unsigned DEST[63:56] ← ABS(SRC[63:56])

PABSB (with 128 bit operands)

Unsigned DEST[7:0] ← ABS(SRC[7:.0])

Repeat operation for 2nd through 15th bytes

Unsigned DEST[127:120] ← ABS(SRC[127:120])

PABSW (with 64 bit operands)

Unsigned DEST[15:0] ← ABS(SRC[15:0])

Repeat operation for 2nd through 3rd 16-bit words

Unsigned DEST[63:48] ← ABS(SRC[63:48])

PABSW (with 128 bit operands)

Unsigned DEST[15:0] ← ABS(SRC[15:0])

Repeat operation for 2nd through 7th 16-bit words

Unsigned DEST[127:112] ← ABS(SRC[127:112])

PABSD (with 64 bit operands)

Unsigned DEST[31:0] ← ABS(SRC[31:0])

Unsigned DEST[63:32] ← ABS(SRC[63:32])

PABSD (with 128 bit operands)

Unsigned DEST[31:0] ← ABS(SRC[31:0])

Repeat operation for 2nd through 3rd 32-bit double words

Unsigned DEST[127:96] ← ABS(SRC[127:96])

PABSB (128-bit Legacy SSE version)

DEST[127:0]  BYTE_ABS(SRC)

DEST[VLMAX-1:128] (Unmodified)

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PABSB/PABSW/PABSD — Packed Absolute Value

INSTRUCTION SET REFERENCE, N-Z

VPABSB (VEX.128 encoded version)

DEST[127:0]  BYTE_ABS(SRC)

DEST[VLMAX-1:128]  0

VPABSB (VEX.256 encoded version)

Unsigned DEST[7:0] ABS(SRC[7:.0])

Repeat operation for 2nd through 31st bytes

Unsigned DEST[255:248]  ABS(SRC[255:248])

PABSW (128-bit Legacy SSE version)

DEST[127:0]  WORD_ABS(SRC)

DEST[VLMAX-1:128] (Unmodified)

VPABSW (VEX.128 encoded version)

DEST[127:0]  WORD_ABS(SRC)

DEST[VLMAX-1:128]  0

VPABSW (VEX.256 encoded version)

Unsigned DEST[15:0] ABS(SRC[15:0])

Repeat operation for 2nd through 15th 16-bit words

Unsigned DEST[255:240]  ABS(SRC[255:240])

PABSD (128-bit Legacy SSE version)

DEST[127:0]  DWORD_ABS(SRC)

DEST[VLMAX-1:128] (Unmodified)

VPABSD (VEX.128 encoded version)

DEST[127:0]  DWORD_ABS(SRC)

DEST[VLMAX-1:128]  0

VPABSD (VEX.256 encoded version)

Unsigned DEST[31:0]  ABS(SRC[31:0])

Repeat operation for 2nd through 7th 32-bit double words

Unsigned DEST[255:224]  ABS(SRC[255:224])

Intel C/C++ Compiler Intrinsic Equivalents

PABSB:

__m64 _mm_abs_pi8 (__m64 a)

(V)PABSB:

__m128i _mm_abs_epi8 (__m128i a)

VPABSB:

__m256i _mm256_abs_epi8 (__m256i a)

PABSW:

__m64 _mm_abs_pi16 (__m64 a)

(V)PABSW:

__m128i _mm_abs_epi16 (__m128i a)

VPABSW:

__m256i _mm256_abs_epi16 (__m256i a)

PABSD:

__m64 _mm_abs_pi32 (__m64 a)

(V)PABSD:

__m128i _mm_abs_epi32 (__m128i a)

VPABSD:

__m256i _mm256_abs_epi32 (__m256i a)

SIMD Floating-Point Exceptions

None.

PABSB/PABSW/PABSD — Packed Absolute Value

Vol. 2B

4-25

INSTRUCTION SET REFERENCE, N-Z

PACKSSWB/PACKSSDW—Pack with Signed Saturation

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

0F 63 /r¹

V/V

MMX

Converts 4 packed signed word integers from

PACKSSWB mm1, mm2/m64

mm1 and from mm2/m64 into 8 packed

signed byte integers in mm1 using signed

saturation.

66 0F 63 /r

V/V

SSE2

Converts 8 packed signed word integers from

xmm1 and from xxm2/m128 into 16 packed

PACKSSWB xmm1, xmm2/m128

signed byte integers in xxm1 using signed

saturation.

0F 6B /r¹

V/V

MMX

Converts 2 packed signed doubleword

integers from mm1 and from mm2/m64 into 4

PACKSSDW mm1, mm2/m64

packed signed word integers in mm1 using

signed saturation.

66 0F 6B /r

V/V

SSE2

Converts 4 packed signed doubleword

integers from xmm1 and from xxm2/m128

PACKSSDW xmm1, xmm2/m128

into 8 packed signed word integers in xxm1

using signed saturation.

VEX.NDS.128.66.0F.WIG 63 /r

RVM

V/V

AVX

Converts 8 packed signed word integers from

xmm2 and from xmm3/m128 into 16 packed

VPACKSSWB xmm1,xmm2, xmm3/m128

signed byte integers in xmm1 using signed

saturation.

VEX.NDS.128.66.0F.WIG 6B /r

RVM

V/V

AVX

Converts 4 packed signed doubleword

integers from xmm2 and from xmm3/m128

VPACKSSDW xmm1,xmm2, xmm3/m128

into 8 packed signed word integers in xmm1

using signed saturation.

VEX.NDS.256.66.0F.WIG 63 /r

RVM

V/V

AVX2

Converts 16 packed signed word integers

VPACKSSWB ymm1, ymm2, ymm3/m256

from ymm2 and from ymm3/m256 into 32

packed signed byte integers in ymm1 using

signed saturation.

VEX.NDS.256.66.0F.WIG 6B /r

RVM

V/V

AVX2

Converts 8 packed signed doubleword

VPACKSSDW ymm1, ymm2, ymm3/m256

integers from ymm2 and from ymm3/m256

into 16 packed signed word integers in

ymm1using signed saturation.

NOTES:

1. See note in Section 2.4, “Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

Description

Converts packed signed word integers into packed signed byte integers (PACKSSWB) or converts packed signed

doubleword integers into packed signed word integers (PACKSSDW), using saturation to handle overflow condi-

tions. See Figure 4-2 for an example of the packing operation.

PACKSSWB/PACKSSDW—Pack with Signed Saturation

Vol. 2B

4-27

INSTRUCTION SET REFERENCE, N-Z

64-Bit SRC

64-Bit DEST

D’

C’

B’

A’

64-Bit DEST

Figure 4-2. Operation of the PACKSSDW Instruction Using 64-bit Operands

The (V)PACKSSWB instruction converts 4, 8 or 16 signed word integers from the destination operand (first

operand) and 4, 8 or 16 signed word integers from the source operand (second operand) into 8, 16 or 32 signed

byte integers and stores the result in the destination operand. If a signed word integer value is beyond the range

of a signed byte integer (that is, greater than 7FH for a positive integer or greater than 80H for a negative integer),

the saturated signed byte integer value of 7FH or 80H, respectively, is stored in the destination.

The (V)PACKSSDW instruction packs 2, 4 or 8 signed doublewords from the destination operand (first operand) and

2, 4 or 8 signed doublewords from the source operand (second operand) into 4, 8 or 16 signed words in the desti-

nation operand (see Figure 4-2). If a signed doubleword integer value is beyond the range of a signed word (that

is, greater than 7FFFH for a positive integer or greater than 8000H for a negative integer), the saturated signed

word integer value of 7FFFH or 8000H, respectively, is stored into the destination.

The (V)PACKSSWB and (V)PACKSSDW instructions operate on either 64-bit, 128-bit operands or 256-bit operands.

When operating on 64-bit operands, the destination operand must be an MMX technology register and the source

operand can be either an MMX technology register or a 64-bit memory location. In 64-bit mode, using a REX prefix

in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation

PACKSSWB (with 64-bit operands)

DEST[7:0] ← SaturateSignedWordToSignedByte DEST[15:0];

DEST[15:8] ← SaturateSignedWordToSignedByte DEST[31:16];

DEST[23:16] ← SaturateSignedWordToSignedByte DEST[47:32];

DEST[31:24] ← SaturateSignedWordToSignedByte DEST[63:48];

DEST[39:32] ← SaturateSignedWordToSignedByte SRC[15:0];

DEST[47:40] ← SaturateSignedWordToSignedByte SRC[31:16];

DEST[55:48] ← SaturateSignedWordToSignedByte SRC[47:32];

DEST[63:56] ← SaturateSignedWordToSignedByte SRC[63:48];

PACKSSDW (with 64-bit operands)

DEST[15:0] ← SaturateSignedDoublewordToSignedWord DEST[31:0];

DEST[31:16] ← SaturateSignedDoublewordToSignedWord DEST[63:32];

DEST[47:32] ← SaturateSignedDoublewordToSignedWord SRC[31:0];

DEST[63:48] ← SaturateSignedDoublewordToSignedWord SRC[63:32];

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PACKSSWB/PACKSSDW—Pack with Signed Saturation

INSTRUCTION SET REFERENCE, N-Z

PACKSSWB instruction (128-bit Legacy SSE version)

DEST[7:0] SaturateSignedWordToSignedByte (DEST[15:0]);

DEST[15:8]  SaturateSignedWordToSignedByte (DEST[31:16]);

DEST[23:16]  SaturateSignedWordToSignedByte (DEST[47:32]);

DEST[31:24]  SaturateSignedWordToSignedByte (DEST[63:48]);

DEST[39:32]  SaturateSignedWordToSignedByte (DEST[79:64]);

DEST[47:40] SaturateSignedWordToSignedByte (DEST[95:80]);

DEST[55:48]  SaturateSignedWordToSignedByte (DEST[111:96]);

DEST[63:56]  SaturateSignedWordToSignedByte (DEST[127:112]);

DEST[71:64]  SaturateSignedWordToSignedByte (SRC[15:0]);

DEST[79:72]  SaturateSignedWordToSignedByte (SRC[31:16]);

DEST[87:80]  SaturateSignedWordToSignedByte (SRC[47:32]);

DEST[95:88]  SaturateSignedWordToSignedByte (SRC[63:48]);

DEST[103:96]  SaturateSignedWordToSignedByte (SRC[79:64]);

DEST[111:104]  SaturateSignedWordToSignedByte (SRC[95:80]);

DEST[119:112]  SaturateSignedWordToSignedByte (SRC[111:96]);

DEST[127:120]  SaturateSignedWordToSignedByte (SRC[127:112]);

PACKSSDW instruction (128-bit Legacy SSE version)

DEST[15:0]  SaturateSignedDwordToSignedWord (DEST[31:0]);

DEST[31:16]  SaturateSignedDwordToSignedWord (DEST[63:32]);

DEST[47:32]  SaturateSignedDwordToSignedWord (DEST[95:64]);

DEST[63:48]  SaturateSignedDwordToSignedWord (DEST[127:96]);

DEST[79:64]  SaturateSignedDwordToSignedWord (SRC[31:0]);

DEST[95:80]  SaturateSignedDwordToSignedWord (SRC[63:32]);

DEST[111:96]  SaturateSignedDwordToSignedWord (SRC[95:64]);

DEST[127:112]  SaturateSignedDwordToSignedWord (SRC[127:96]);

VPACKSSWB instruction (VEX.128 encoded version)

DEST[7:0] SaturateSignedWordToSignedByte (SRC1[15:0]);

DEST[15:8]  SaturateSignedWordToSignedByte (SRC1[31:16]);

DEST[23:16]  SaturateSignedWordToSignedByte (SRC1[47:32]);

DEST[31:24]  SaturateSignedWordToSignedByte (SRC1[63:48]);

DEST[39:32]  SaturateSignedWordToSignedByte (SRC1[79:64]);

DEST[47:40]  SaturateSignedWordToSignedByte (SRC1[95:80]);

DEST[55:48]  SaturateSignedWordToSignedByte (SRC1[111:96]);

DEST[63:56]  SaturateSignedWordToSignedByte (SRC1[127:112]);

DEST[71:64]  SaturateSignedWordToSignedByte (SRC2[15:0]);

DEST[79:72]  SaturateSignedWordToSignedByte (SRC2[31:16]);

DEST[87:80]  SaturateSignedWordToSignedByte (SRC2[47:32]);

DEST[95:88]  SaturateSignedWordToSignedByte (SRC2[63:48]);

DEST[103:96]  SaturateSignedWordToSignedByte (SRC2[79:64]);

DEST[111:104]  SaturateSignedWordToSignedByte (SRC2[95:80]);

DEST[119:112]  SaturateSignedWordToSignedByte (SRC2[111:96]);

DEST[127:120]  SaturateSignedWordToSignedByte (SRC2[127:112]);

DEST[VLMAX-1:128] 0;

VPACKSSDW instruction (VEX.128 encoded version)

DEST[15:0]  SaturateSignedDwordToSignedWord (SRC1[31:0]);

DEST[31:16]  SaturateSignedDwordToSignedWord (SRC1[63:32]);

DEST[47:32]  SaturateSignedDwordToSignedWord (SRC1[95:64]);

DEST[63:48]  SaturateSignedDwordToSignedWord (SRC1[127:96]);

DEST[79:64]  SaturateSignedDwordToSignedWord (SRC2[31:0]);

DEST[95:80]  SaturateSignedDwordToSignedWord (SRC2[63:32]);

PACKSSWB/PACKSSDW—Pack with Signed Saturation

Vol. 2B

4-29

INSTRUCTION SET REFERENCE, N-Z

DEST[111:96]  SaturateSignedDwordToSignedWord (SRC2[95:64]);

DEST[127:112]  SaturateSignedDwordToSignedWord (SRC2[127:96]);

DEST[VLMAX-1:128] 0;

VPACKSSWB instruction (VEX.256 encoded version)

DEST[7:0] SaturateSignedWordToSignedByte (SRC1[15:0]);

DEST[15:8]  SaturateSignedWordToSignedByte (SRC1[31:16]);

DEST[23:16]  SaturateSignedWordToSignedByte (SRC1[47:32]);

DEST[31:24]  SaturateSignedWordToSignedByte (SRC1[63:48]);

DEST[39:32]  SaturateSignedWordToSignedByte (SRC1[79:64]);

DEST[47:40]  SaturateSignedWordToSignedByte (SRC1[95:80]);

DEST[55:48]  SaturateSignedWordToSignedByte (SRC1[111:96]);

DEST[63:56]  SaturateSignedWordToSignedByte (SRC1[127:112]);

DEST[71:64]  SaturateSignedWordToSignedByte (SRC2[15:0]);

DEST[79:72]  SaturateSignedWordToSignedByte (SRC2[31:16]);

DEST[87:80]  SaturateSignedWordToSignedByte (SRC2[47:32]);

DEST[95:88]  SaturateSignedWordToSignedByte (SRC2[63:48]);

DEST[103:96]  SaturateSignedWordToSignedByte (SRC2[79:64]);

DEST[111:104]  SaturateSignedWordToSignedByte (SRC2[95:80]);

DEST[119:112]  SaturateSignedWordToSignedByte (SRC2[111:96]);

DEST[127:120]  SaturateSignedWordToSignedByte (SRC2[127:112]);

DEST[135:128] SaturateSignedWordToSignedByte (SRC1[143:128]);

DEST[143:136]  SaturateSignedWordToSignedByte (SRC1[159:144]);

DEST[151:144]  SaturateSignedWordToSignedByte (SRC1[175:160]);

DEST[159:152]  SaturateSignedWordToSignedByte (SRC1[191:176]);

DEST[167:160]  SaturateSignedWordToSignedByte (SRC1[207:192]);

DEST[175:168]  SaturateSignedWordToSignedByte (SRC1[223:208]);

DEST[183:176]  SaturateSignedWordToSignedByte (SRC1[239:224]);

DEST[191:184]  SaturateSignedWordToSignedByte (SRC1[255:240]);

DEST[199:192]  SaturateSignedWordToSignedByte (SRC2[143:128]);

DEST[207:200]  SaturateSignedWordToSignedByte (SRC2[159:144]);

DEST[215:208]  SaturateSignedWordToSignedByte (SRC2[175:160]);

DEST[223:216]  SaturateSignedWordToSignedByte (SRC2[191:176]);

DEST[231:224]  SaturateSignedWordToSignedByte (SRC2[207:192]);

DEST[239:232]  SaturateSignedWordToSignedByte (SRC2[223:208]);

DEST[247:240]  SaturateSignedWordToSignedByte (SRC2[239:224]);

DEST[255:248]  SaturateSignedWordToSignedByte (SRC2[255:240]);

VPACKSSDW instruction (VEX.256 encoded version)

DEST[15:0]  SaturateSignedDwordToSignedWord (SRC1[31:0]);

DEST[31:16]  SaturateSignedDwordToSignedWord (SRC1[63:32]);

DEST[47:32]  SaturateSignedDwordToSignedWord (SRC1[95:64]);

DEST[63:48]  SaturateSignedDwordToSignedWord (SRC1[127:96]);

DEST[79:64]  SaturateSignedDwordToSignedWord (SRC2[31:0]);

DEST[95:80]  SaturateSignedDwordToSignedWord (SRC2[63:32]);

DEST[111:96]  SaturateSignedDwordToSignedWord (SRC2[95:64]);

DEST[127:112]  SaturateSignedDwordToSignedWord (SRC2[127:96]);

DEST[143:128]  SaturateSignedDwordToSignedWord (SRC1[159:128]);

DEST[159:144]  SaturateSignedDwordToSignedWord (SRC1[191:160]);

DEST[175:160]  SaturateSignedDwordToSignedWord (SRC1[223:192]);

DEST[191:176]  SaturateSignedDwordToSignedWord (SRC1[255:224]);

DEST[207:192]  SaturateSignedDwordToSignedWord (SRC2[159:128]);

DEST[223:208]  SaturateSignedDwordToSignedWord (SRC2[191:160]);

DEST[239:224]  SaturateSignedDwordToSignedWord (SRC2[223:192]);

4-30

Vol. 2B

PACKSSWB/PACKSSDW—Pack with Signed Saturation

INSTRUCTION SET REFERENCE, N-Z

PACKUSDW — Pack with Unsigned Saturation

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

66 0F 38 2B /r

RM V/V

SSE4_1

Convert 4 packed signed doubleword integers

PACKUSDW xmm1, xmm2/m128

from xmm1 and 4 packed signed doubleword

integers from xmm2/m128 into 8 packed

unsigned word integers in xmm1 using

unsigned saturation.

VEX.NDS.128.66.0F38.WIG 2B /r

RVM V/V

AVX

Convert 4 packed signed doubleword integers

VPACKUSDW xmm1, xmm2, xmm3/m128

from xmm2 and 4 packed signed doubleword

integers from xmm3/m128 into 8 packed

unsigned word integers in xmm1 using

unsigned saturation.

VEX.NDS.256.66.0F38.WIG 2B /r

RVM V/V

AVX2

Convert 8 packed signed doubleword integers

VPACKUSDW ymm1, ymm2, ymm3/m256

from ymm2 and 8 packed signed doubleword

integers from ymm3/m128 into 16 packed

unsigned word integers in ymm1 using

unsigned saturation.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

Description

Converts packed signed doubleword integers into packed unsigned word integers using unsigned saturation to

handle overflow conditions. If the signed doubleword value is beyond the range of an unsigned word (that is,

greater than FFFFH or less than 0000H), the saturated unsigned word integer value of FFFFH or 0000H, respec-

tively, is stored in the destination.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation

PACKUSDW (Legacy SSE instruction)

TMP[15:0]  (DEST[31:0] < 0) ? 0 : DEST[15:0];

DEST[15:0]  (DEST[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;

TMP[31:16]  (DEST[63:32] < 0) ? 0 : DEST[47:32];

DEST[31:16]  (DEST[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;

TMP[47:32]  (DEST[95:64] < 0) ? 0 : DEST[79:64];

DEST[47:32]  (DEST[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;

TMP[63:48]  (DEST[127:96] < 0) ? 0 : DEST[111:96];

DEST[63:48]  (DEST[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;

TMP[79:64]  (SRC[31:0] < 0) ? 0 : SRC[15:0];

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PACKUSDW — Pack with Unsigned Saturation

INSTRUCTION SET REFERENCE, N-Z

DEST[63:48]  (SRC[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;

TMP[95:80]  (SRC[63:32] < 0) ? 0 : SRC[47:32];

DEST[95:80]  (SRC[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;

TMP[111:96]  (SRC[95:64] < 0) ? 0 : SRC[79:64];

DEST[111:96]  (SRC[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;

TMP[127:112]  (SRC[127:96] < 0) ? 0 : SRC[111:96];

DEST[127:112]  (SRC[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;

PACKUSDW (VEX.128 encoded version)

TMP[15:0]  (SRC1[31:0] < 0) ? 0 : SRC1[15:0];

DEST[15:0]  (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;

TMP[31:16]  (SRC1[63:32] < 0) ? 0 : SRC1[47:32];

DEST[31:16]  (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;

TMP[47:32]  (SRC1[95:64] < 0) ? 0 : SRC1[79:64];

DEST[47:32]  (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;

TMP[63:48]  (SRC1[127:96] < 0) ? 0 : SRC1[111:96];

DEST[63:48]  (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;

TMP[79:64]  (SRC2[31:0] < 0) ? 0 : SRC2[15:0];

DEST[63:48]  (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;

TMP[95:80]  (SRC2[63:32] < 0) ? 0 : SRC2[47:32];

DEST[95:80]  (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;

TMP[111:96]  (SRC2[95:64] < 0) ? 0 : SRC2[79:64];

DEST[111:96]  (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;

TMP[127:112]  (SRC2[127:96] < 0) ? 0 : SRC2[111:96];

DEST[127:112]  (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112];

DEST[VLMAX-1:128]  0;

VPACKUSDW (VEX.256 encoded version)

TMP[15:0]  (SRC1[31:0] < 0) ? 0 : SRC1[15:0];

DEST[15:0]  (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;

TMP[31:16]  (SRC1[63:32] < 0) ? 0 : SRC1[47:32];

DEST[31:16]  (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;

TMP[47:32]  (SRC1[95:64] < 0) ? 0 : SRC1[79:64];

DEST[47:32]  (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;

TMP[63:48]  (SRC1[127:96] < 0) ? 0 : SRC1[111:96];

DEST[63:48]  (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;

TMP[79:64]  (SRC2[31:0] < 0) ? 0 : SRC2[15:0];

DEST[63:48]  (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;

TMP[95:80]  (SRC2[63:32] < 0) ? 0 : SRC2[47:32];

DEST[95:80]  (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;

TMP[111:96]  (SRC2[95:64] < 0) ? 0 : SRC2[79:64];

DEST[111:96]  (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;

TMP[127:112]  (SRC2[127:96] < 0) ? 0 : SRC2[111:96];

DEST[128:112]  (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;

TMP[143:128]  (SRC1[159:128] < 0) ? 0 : SRC1[143:128];

DEST[143:128]  (SRC1[159:128] > FFFFH) ? FFFFH : TMP[143:128] ;

TMP[159:144]  (SRC1[191:160] < 0) ? 0 : SRC1[175:160];

DEST[159:144]  (SRC1[191:160] > FFFFH) ? FFFFH : TMP[159:144] ;

TMP[175:160]  (SRC1[223:192] < 0) ? 0 : SRC1[207:192];

DEST[175:160]  (SRC1[223:192] > FFFFH) ? FFFFH : TMP[175:160] ;

TMP[191:176]  (SRC1[255:224] < 0) ? 0 : SRC1[239:224];

DEST[191:176]  (SRC1[255:224] > FFFFH) ? FFFFH : TMP[191:176] ;

TMP[207:192]  (SRC2[159:128] < 0) ? 0 : SRC2[143:128];

DEST[207:192]  (SRC2[159:128] > FFFFH) ? FFFFH : TMP[207:192] ;

PACKUSDW — Pack with Unsigned Saturation

Vol. 2B

4-33

INSTRUCTION SET REFERENCE, N-Z

PACKUSWB—Pack with Unsigned Saturation

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

0F 67 /r¹

RM V/V

MMX

Converts 4 signed word integers from mm and

4 signed word integers from mm/m64 into 8

PACKUSWB mm, mm/m64

unsigned byte integers in mm using unsigned

saturation.

66 0F 67 /r

RM V/V

SSE2

Converts 8 signed word integers from xmm1

and 8 signed word integers from xmm2/m128

PACKUSWB xmm1, xmm2/m128

into 16 unsigned byte integers in xmm1 using

unsigned saturation.

VEX.NDS.128.66.0F.WIG 67 /r

RVM V/V

AVX

Converts 8 signed word integers from xmm2

and 8 signed word integers from xmm3/m128

VPACKUSWB xmm1, xmm2, xmm3/m128

into 16 unsigned byte integers in xmm1 using

unsigned saturation.

VEX.NDS.256.66.0F.WIG 67 /r

RVM V/V

AVX2

Converts 16 signed word integers from ymm2

and 16signed word integers from

VPACKUSWB ymm1, ymm2, ymm3/m256

ymm3/m256 into 32 unsigned byte integers

in ymm1 using unsigned saturation.

NOTES:

1. See note in Section 2.4, “Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

Description

Converts 4, 8 or 16 signed word integers from the destination operand (first operand) and 4, 8 or 16 signed word

integers from the source operand (second operand) into 8, 16 or 32 unsigned byte integers and stores the result in

the destination operand. (See Figure 4-2 for an example of the packing operation.) If a signed word integer value

is beyond the range of an unsigned byte integer (that is, greater than FFH or less than 00H), the saturated

unsigned byte integer value of FFH or 00H, respectively, is stored in the destination.

The PACKUSWB instruction operates on either 64-bit, 128-bit or 256-bit operands. When operating on 64-bit oper-

ands, the destination operand must be an MMX technology register and the source operand can be either an MMX

technology register or a 64-bit memory location. In 64-bit mode, using a REX prefix in the form of REX.R permits

this instruction to access additional registers (XMM8-XMM15).

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

PACKUSWB—Pack with Unsigned Saturation

Vol. 2B

4-35

INSTRUCTION SET REFERENCE, N-Z

Operation

PACKUSWB (with 64-bit operands)

DEST[7:0] ← SaturateSignedWordToUnsignedByte DEST[15:0];

DEST[15:8] ← SaturateSignedWordToUnsignedByte DEST[31:16];

DEST[23:16] ← SaturateSignedWordToUnsignedByte DEST[47:32];

DEST[31:24] ← SaturateSignedWordToUnsignedByte DEST[63:48];

DEST[39:32] ← SaturateSignedWordToUnsignedByte SRC[15:0];

DEST[47:40] ← SaturateSignedWordToUnsignedByte SRC[31:16];

DEST[55:48] ← SaturateSignedWordToUnsignedByte SRC[47:32];

DEST[63:56] ← SaturateSignedWordToUnsignedByte SRC[63:48];

PACKUSWB (Legacy SSE instruction)

DEST[7:0]SaturateSignedWordToUnsignedByte (DEST[15:0]);

DEST[15:8] SaturateSignedWordToUnsignedByte (DEST[31:16]);

DEST[23:16] SaturateSignedWordToUnsignedByte (DEST[47:32]);

DEST[31:24]  SaturateSignedWordToUnsignedByte (DEST[63:48]);

DEST[39:32]  SaturateSignedWordToUnsignedByte (DEST[79:64]);

DEST[47:40]  SaturateSignedWordToUnsignedByte (DEST[95:80]);

DEST[55:48]  SaturateSignedWordToUnsignedByte (DEST[111:96]);

DEST[63:56]  SaturateSignedWordToUnsignedByte (DEST[127:112]);

DEST[71:64]  SaturateSignedWordToUnsignedByte (SRC[15:0]);

DEST[79:72]  SaturateSignedWordToUnsignedByte (SRC[31:16]);

DEST[87:80]  SaturateSignedWordToUnsignedByte (SRC[47:32]);

DEST[95:88]  SaturateSignedWordToUnsignedByte (SRC[63:48]);

DEST[103:96]  SaturateSignedWordToUnsignedByte (SRC[79:64]);

DEST[111:104]  SaturateSignedWordToUnsignedByte (SRC[95:80]);

DEST[119:112]  SaturateSignedWordToUnsignedByte (SRC[111:96]);

DEST[127:120]  SaturateSignedWordToUnsignedByte (SRC[127:112]);

PACKUSWB (VEX.128 encoded version)

DEST[7:0] SaturateSignedWordToUnsignedByte (SRC1[15:0]);

DEST[15:8] SaturateSignedWordToUnsignedByte (SRC1[31:16]);

DEST[23:16] SaturateSignedWordToUnsignedByte (SRC1[47:32]);

DEST[31:24]  SaturateSignedWordToUnsignedByte (SRC1[63:48]);

DEST[39:32]  SaturateSignedWordToUnsignedByte (SRC1[79:64]);

DEST[47:40]  SaturateSignedWordToUnsignedByte (SRC1[95:80]);

DEST[55:48]  SaturateSignedWordToUnsignedByte (SRC1[111:96]);

DEST[63:56]  SaturateSignedWordToUnsignedByte (SRC1[127:112]);

DEST[71:64]  SaturateSignedWordToUnsignedByte (SRC2[15:0]);

DEST[79:72]  SaturateSignedWordToUnsignedByte (SRC2[31:16]);

DEST[87:80]  SaturateSignedWordToUnsignedByte (SRC2[47:32]);

DEST[95:88]  SaturateSignedWordToUnsignedByte (SRC2[63:48]);

DEST[103:96]  SaturateSignedWordToUnsignedByte (SRC2[79:64]);

DEST[111:104]  SaturateSignedWordToUnsignedByte (SRC2[95:80]);

DEST[119:112]  SaturateSignedWordToUnsignedByte (SRC2[111:96]);

DEST[127:120]  SaturateSignedWordToUnsignedByte (SRC2[127:112]);

DEST[VLMAX-1:128]  0;

VPACKUSWB (VEX.256 encoded version)

DEST[7:0] SaturateSignedWordToUnsignedByte (SRC1[15:0]);

DEST[15:8] SaturateSignedWordToUnsignedByte (SRC1[31:16]);

DEST[23:16] SaturateSignedWordToUnsignedByte (SRC1[47:32]);

DEST[31:24]  SaturateSignedWordToUnsignedByte (SRC1[63:48]);

DEST[39:32] SaturateSignedWordToUnsignedByte (SRC1[79:64]);

4-36

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PACKUSWB—Pack with Unsigned Saturation

INSTRUCTION SET REFERENCE, N-Z

DEST[47:40]  SaturateSignedWordToUnsignedByte (SRC1[95:80]);

DEST[55:48]  SaturateSignedWordToUnsignedByte (SRC1[111:96]);

DEST[63:56]  SaturateSignedWordToUnsignedByte (SRC1[127:112]);

DEST[71:64] SaturateSignedWordToUnsignedByte (SRC2[15:0]);

DEST[79:72]  SaturateSignedWordToUnsignedByte (SRC2[31:16]);

DEST[87:80]  SaturateSignedWordToUnsignedByte (SRC2[47:32]);

DEST[95:88]  SaturateSignedWordToUnsignedByte (SRC2[63:48]);

DEST[103:96]  SaturateSignedWordToUnsignedByte (SRC2[79:64]);

DEST[111:104]  SaturateSignedWordToUnsignedByte (SRC2[95:80]);

DEST[119:112]  SaturateSignedWordToUnsignedByte (SRC2[111:96]);

DEST[127:120]  SaturateSignedWordToUnsignedByte (SRC2[127:112]);

DEST[135:128] SaturateSignedWordToUnsignedByte (SRC1[143:128]);

DEST[143:136] SaturateSignedWordToUnsignedByte (SRC1[159:144]);

DEST[151:144] SaturateSignedWordToUnsignedByte (SRC1[175:160]);

DEST[159:152] SaturateSignedWordToUnsignedByte (SRC1[191:176]);

DEST[167:160]  SaturateSignedWordToUnsignedByte (SRC1[207:192]);

DEST[175:168]  SaturateSignedWordToUnsignedByte (SRC1[223:208]);

DEST[183:176]  SaturateSignedWordToUnsignedByte (SRC1[239:224]);

DEST[191:184]  SaturateSignedWordToUnsignedByte (SRC1[255:240]);

DEST[199:192]  SaturateSignedWordToUnsignedByte (SRC2[143:128]);

DEST[207:200]  SaturateSignedWordToUnsignedByte (SRC2[159:144]);

DEST[215:208]  SaturateSignedWordToUnsignedByte (SRC2[175:160]);

DEST[223:216]  SaturateSignedWordToUnsignedByte (SRC2[191:176]);

DEST[231:224]  SaturateSignedWordToUnsignedByte (SRC2[207:192]);

DEST[239:232]  SaturateSignedWordToUnsignedByte (SRC2[223:208]);

DEST[247:240]  SaturateSignedWordToUnsignedByte (SRC2[239:224]);

DEST[255:248]  SaturateSignedWordToUnsignedByte (SRC2[255:240]);

Intel C/C++ Compiler Intrinsic Equivalent

PACKUSWB:

__m64 _mm_packs_pu16(__m64 m1, __m64 m2)

(V)PACKUSWB:

__m128i _mm_packus_epi16(__m128i m1, __m128i m2)

VPACKUSWB:

__m256i _mm256_packus_epi16(__m256i m1, __m256i m2);

Flags Affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Exceptions Type 4; additionally

#UD

If VEX.L = 1.

PACKUSWB—Pack with Unsigned Saturation

Vol. 2B

4-37

INSTRUCTION SET REFERENCE, N-Z

PADDB/PADDW/PADDD—Add Packed Integers

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

0F FC /r¹

V/V

MMX

Add packed byte integers from mm/m64 and

mm.

PADDB mm, mm/m64

66 0F FC /r

V/V

SSE2

Add packed byte integers from xmm2/m128

and xmm1.

PADDB xmm1, xmm2/m128

0F FD /r¹

V/V

MMX

Add packed word integers from mm/m64 and

mm.

PADDW mm, mm/m64

66 0F FD /r

V/V

SSE2

Add packed word integers from xmm2/m128

and xmm1.

PADDW xmm1, xmm2/m128

0F FE /r¹

V/V

MMX

Add packed doubleword integers from

mm/m64 and mm.

PADDD mm, mm/m64

66 0F FE /r

V/V

SSE2

Add packed doubleword integers from

xmm2/m128 and xmm1.

PADDD xmm1, xmm2/m128

VEX.NDS.128.66.0F.WIG FC /r

RVM

V/V

AVX

Add packed byte integers from xmm3/m128

and xmm2.

VPADDB xmm1, xmm2, xmm3/m128

VEX.NDS.128.66.0F.WIG FD /r

RVM

V/V

AVX

Add packed word integers from xmm3/m128

and xmm2.

VPADDW xmm1, xmm2, xmm3/m128

VEX.NDS.128.66.0F.WIG FE /r

RVM

V/V

AVX

Add packed doubleword integers from

xmm3/m128 and xmm2.

VPADDD xmm1, xmm2, xmm3/m128

VEX.NDS.256.66.0F.WIG FC /r

RVM

V/V

AVX2

Add packed byte integers from ymm2, and

ymm3/m256 and store in ymm1.

VPADDB ymm1, ymm2, ymm3/m256

VEX.NDS.256.66.0F.WIG FD /r

RVM

V/V

AVX2

Add packed word integers from ymm2,

ymm3/m256 and store in ymm1.

VPADDW ymm1, ymm2, ymm3/m256

VEX.NDS.256.66.0F.WIG FE /r

RVM

V/V

AVX2

Add packed doubleword integers from ymm2,

ymm3/m256 and store in ymm1.

VPADDD ymm1, ymm2, ymm3/m256

NOTES:

1. See note in Section 2.4, “Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

Description

Performs a SIMD add of the packed integers from the source operand (second operand) and the destination

operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD operation.

Overflow is handled with wraparound, as described in the following paragraphs.

Adds the packed byte, word, doubleword, or quadword integers in the first source operand to the second source

operand and stores the result in the destination operand. When a result is too large to be represented in the

4-38

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PADDB/PADDW/PADDD—Add Packed Integers

INSTRUCTION SET REFERENCE, N-Z

8/16/32 integer (overflow), the result is wrapped around and the low bits are written to the destination element

(that is, the carry is ignored).

Note that these instructions can operate on either unsigned or signed (two’s complement notation) integers;

however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected

overflow conditions, software must control the ranges of the values operated on.

These instructions can operate on either 64-bit, 128-bit or 256-bit operands. When operating on 64-bit operands,

the destination operand must be an MMX technology register and the source operand can be either an MMX tech-

nology register or a 64-bit memory location. In 64-bit mode, using a REX prefix in the form of REX.R permits this

instruction to access additional registers (XMM8-XMM15).

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation

PADDB (with 64-bit operands)

DEST[7:0] ← DEST[7:0] + SRC[7:0];

(* Repeat add operation for 2nd through 7th byte *)

DEST[63:56] ← DEST[63:56] + SRC[63:56];

PADDB (with 128-bit operands)

DEST[7:0] ← DEST[7:0] + SRC[7:0];

(* Repeat add operation for 2nd through 14th byte *)

DEST[127:120] ← DEST[111:120] + SRC[127:120];

VPADDB (VEX.128 encoded version)

DEST[7:0]  SRC1[7:0]+SRC2[7:0]

DEST[15:8]  SRC1[15:8]+SRC2[15:8]

DEST[23:16]  SRC1[23:16]+SRC2[23:16]

DEST[31:24]  SRC1[31:24]+SRC2[31:24]

DEST[39:32]  SRC1[39:32]+SRC2[39:32]

DEST[47:40]  SRC1[47:40]+SRC2[47:40]

DEST[55:48]  SRC1[55:48]+SRC2[55:48]

DEST[63:56]  SRC1[63:56]+SRC2[63:56]

DEST[71:64]  SRC1[71:64]+SRC2[71:64]

DEST[79:72]  SRC1[79:72]+SRC2[79:72]

DEST[87:80]  SRC1[87:80]+SRC2[87:80]

DEST[95:88]  SRC1[95:88]+SRC2[95:88]

DEST[103:96]  SRC1[103:96]+SRC2[103:96]

DEST[111:104]  SRC1[111:104]+SRC2[111:104]

DEST[119:112]  SRC1[119:112]+SRC2[119:112]

DEST[127:120]  SRC1[127:120]+SRC2[127:120]

DEST[VLMAX-1:128]  0

VPADDB (VEX.256 encoded instruction)

DEST[7:0] SRC1[7:0] + SRC2[7:0];

(* Repeat add operation for 2nd through 31th byte *)

DEST[255:248] SRC1[255:248] + SRC2[255:248];

PADDB/PADDW/PADDD—Add Packed Integers

Vol. 2B

4-39

INSTRUCTION SET REFERENCE, N-Z

PADDW (with 64-bit operands)

DEST[15:0] ← DEST[15:0] + SRC[15:0];

(* Repeat add operation for 2nd and 3th word *)

DEST[63:48] ← DEST[63:48] + SRC[63:48];

PADDW (with 128-bit operands)

DEST[15:0] ← DEST[15:0] + SRC[15:0];

(* Repeat add operation for 2nd through 7th word *)

DEST[127:112] ← DEST[127:112] + SRC[127:112];

VPADDW (VEX.128 encoded version)

DEST[15:0]  SRC1[15:0]+SRC2[15:0]

DEST[31:16]  SRC1[31:16]+SRC2[31:16]

DEST[47:32]  SRC1[47:32]+SRC2[47:32]

DEST[63:48]  SRC1[63:48]+SRC2[63:48]

DEST[79:64]  SRC1[79:64]+SRC2[79:64]

DEST[95:80]  SRC1[95:80]+SRC2[95:80]

DEST[111:96]  SRC1[111:96]+SRC2[111:96]

DEST[127:112]  SRC1[127:112]+SRC2[127:112]

DEST[VLMAX-1:128]  0

VPADDW (VEX.256 encoded instruction)

DEST[15:0]  SRC1[15:0] + SRC2[15:0];

(* Repeat add operation for 2nd through 15th word *)

DEST[255:240] SRC1[255:240] + SRC2[255:240];

PADDD (with 64-bit operands)

DEST[31:0] ← DEST[31:0] + SRC[31:0];

DEST[63:32] ← DEST[63:32] + SRC[63:32];

PADDD (with 128-bit operands)

DEST[31:0] ← DEST[31:0] + SRC[31:0];

(* Repeat add operation for 2nd and 3th doubleword *)

DEST[127:96] ← DEST[127:96] + SRC[127:96];

VPADDD (VEX.128 encoded version)

DEST[31:0]  SRC1[31:0]+SRC2[31:0]

DEST[63:32]  SRC1[63:32]+SRC2[63:32]

DEST[95:64]  SRC1[95:64]+SRC2[95:64]

DEST[127:96]  SRC1[127:96]+SRC2[127:96]

DEST[VLMAX-1:128]  0

VPADDD (VEX.256 encoded instruction)

DEST[31:0] SRC1[31:0] + SRC2[31:0];

(* Repeat add operation for 2nd and 7th doubleword *)

DEST[255:224]  SRC1[255:224] + SRC2[255:224];

Intel C/C++ Compiler Intrinsic Equivalents

PADDB:

__m64 _mm_add_pi8(__m64 m1, __m64 m2)

(V)PADDB:

__m128i _mm_add_epi8 (__m128ia,__m128ib )

VPADDB:

__m256i _mm256_add_epi8 (__m256ia,__m256i b )

PADDW:

__m64 _mm_add_pi16(__m64 m1, __m64 m2)

(V)PADDW:

__m128i _mm_add_epi16 ( __m128i a, __m128i b)

4-40

Vol. 2B

PADDB/PADDW/PADDD—Add Packed Integers

INSTRUCTION SET REFERENCE, N-Z

PADDQ—Add Packed Quadword Integers

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

0F D4 /r¹

RM V/V

SSE2

Add quadword integer mm2/m64 to mm1.

PADDQ mm1, mm2/m64

66 0F D4 /r

RM V/V

SSE2

Add packed quadword integers xmm2/m128

to xmm1.

PADDQ xmm1, xmm2/m128

VEX.NDS.128.66.0F.WIG D4 /r

RVM V/V

AVX

Add packed quadword integers xmm3/m128

and xmm2.

VPADDQ xmm1, xmm2, xmm3/m128

VEX.NDS.256.66.0F.WIG D4 /r

RVM V/V

AVX2

Add packed quadword integers from ymm2,

ymm3/m256 and store in ymm1.

VPADDQ ymm1, ymm2, ymm3/m256

NOTES:

1. See note in Section 2.4, “Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

Description

Adds the first operand (destination operand) to the second operand (source operand) and stores the result in the

destination operand. The source operand can be a quadword integer stored in an MMX technology register or a 64-

bit memory location, or it can be two packed quadword integers stored in an XMM register or an 128-bit memory

location. The destination operand can be a quadword integer stored in an MMX technology register or two packed

quadword integers stored in an XMM register. When packed quadword operands are used, a SIMD add is

performed. When a quadword result is too large to be represented in 64 bits (overflow), the result is wrapped

around and the low 64 bits are written to the destination element (that is, the carry is ignored).

Note that the (V)PADDQ instruction can operate on either unsigned or signed (two’s complement notation) inte-

gers; however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected

overflow conditions, software must control the ranges of the values operated on.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers

(XMM8-XMM15).

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation

PADDQ (with 64-Bit operands)

DEST[63:0] ← DEST[63:0] + SRC[63:0];

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PADDQ—Add Packed Quadword Integers

INSTRUCTION SET REFERENCE, N-Z

PADDQ (with 128-Bit operands)

DEST[63:0] ← DEST[63:0] + SRC[63:0];

DEST[127:64] ← DEST[127:64] + SRC[127:64];

VPADDQ (VEX.128 encoded instruction)

DEST[63:0] SRC1[63:0] + SRC2[63:0];

DEST[127:64]  SRC1[127:64] + SRC2[127:64];

DEST[VLMAX-1:128]  0;

VPADDQ (VEX.256 encoded instruction)

DEST[63:0] SRC1[63:0] + SRC2[63:0];

DEST[127:64]  SRC1[127:64] + SRC2[127:64];

DEST[191:128] SRC1[191:128] + SRC2[191:128];

DEST[255:192]  SRC1[255:192] + SRC2[255:192];

Intel C/C++ Compiler Intrinsic Equivalents

PADDQ:

__m64 _mm_add_si64 (__m64 a, __m64 b)

(V)PADDQ:

__m128i _mm_add_epi64 ( __m128i a, __m128i b)

VPADDQ:

__m256i _mm256_add_epi64 ( __m256i a, __m256i b)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

See Exceptions Type 4; additionally

#UD

If VEX.L = 1.

PADDQ—Add Packed Quadword Integers

Vol. 2B

4-43

INSTRUCTION SET REFERENCE, N-Z

PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

0F EC /r¹

RM V/V

MMX

Add packed signed byte integers from

mm/m64 and mm and saturate the results.

PADDSB mm, mm/m64

66 0F EC /r

RM V/V

SSE2

Add packed signed byte integers from

xmm2/m128 and xmm1 saturate the results.

PADDSB xmm1, xmm2/m128

0F ED /r¹

RM V/V

MMX

Add packed signed word integers from

mm/m64 and mm and saturate the results.

PADDSW mm, mm/m64

66 0F ED /r

RM V/V

SSE2

Add packed signed word integers from

xmm2/m128 and xmm1 and saturate the

PADDSW xmm1, xmm2/m128

results.

VEX.NDS.128.66.0F.WIG EC /r

RVM V/V

AVX

Add packed signed byte integers from

VPADDSB xmm1, xmm2, xmm3/m128

xmm3/m128 and xmm2 saturate the results.

VEX.NDS.128.66.0F.WIG ED /r

RVM V/V

AVX

Add packed signed word integers from

xmm3/m128 and xmm2 and saturate the

VPADDSW xmm1, xmm2, xmm3/m128

results.

VEX.NDS.256.66.0F.WIG EC /r

RVM V/V

AVX2

Add packed signed byte integers from ymm2,

VPADDSB ymm1, ymm2, ymm3/m256

and ymm3/m256 and store the saturated

results in ymm1.

VEX.NDS.256.66.0F.WIG ED /r

RVM V/V

AVX2

Add packed signed word integers from ymm2,

and ymm3/m256 and store the saturated

VPADDSW ymm1, ymm2, ymm3/m256

results in ymm1.

NOTES:

1. See note in Section 2.4, “Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

Description

Performs a SIMD add of the packed signed integers from the source operand (second operand) and the destination

operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD operation.

Overflow is handled with signed saturation, as described in the following paragraphs.

The PADDSB instruction adds packed signed byte integers. When an individual byte result is beyond the range of a

signed byte integer (that is, greater than 7FH or less than 80H), the saturated value of 7FH or 80H, respectively, is

written to the destination operand.

The PADDSW instruction adds packed signed word integers. When an individual word result is beyond the range of

a signed word integer (that is, greater than 7FFFH or less than 8000H), the saturated value of 7FFFH or 8000H,

respectively, is written to the destination operand.

These instructions can operate on either 64-bit, 128-bit or 256-bit operands. When operating on 64-bit operands,

the destination operand must be an MMX technology register and the source operand can be either an MMX tech-

nology register or a 64-bit memory location. In 64-bit mode, using a REX prefix in the form of REX.R permits this

instruction to access additional registers (XMM8-XMM15).

4-44

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PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation

INSTRUCTION SET REFERENCE, N-Z

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation

PADDSB (with 64-bit operands)

DEST[7:0] ← SaturateToSignedByte(DEST[7:0] + SRC (7:0]);

(* Repeat add operation for 2nd through 7th bytes *)

DEST[63:56] ← SaturateToSignedByte(DEST[63:56] + SRC[63:56] );

PADDSB (with 128-bit operands)

DEST[7:0] ←SaturateToSignedByte (DEST[7:0] + SRC[7:0]);

(* Repeat add operation for 2nd through 14th bytes *)

DEST[127:120] ← SaturateToSignedByte (DEST[111:120] + SRC[127:120]);

VPADDSB (VEX.128 encoded version)

DEST[7:0]  SaturateToSignedByte (SRC1[7:0] + SRC2[7:0]);

(* Repeat subtract operation for 2nd through 14th bytes *)

DEST[127:120]  SaturateToSignedByte (SRC1[111:120] + SRC2[127:120]);

DEST[VLMAX-1:128]  0

VPADDSB (VEX.256 encoded version)

DEST[7:0]  SaturateToSignedByte (SRC1[7:0] + SRC2[7:0]);

(* Repeat add operation for 2nd through 31st bytes *)

DEST[255:248] SaturateToSignedByte (SRC1[255:248] + SRC2[255:248]);

PADDSW (with 64-bit operands)

DEST[15:0] ← SaturateToSignedWord(DEST[15:0] + SRC[15:0] );

(* Repeat add operation for 2nd and 7th words *)

DEST[63:48] ← SaturateToSignedWord(DEST[63:48] + SRC[63:48] );

PADDSW (with 128-bit operands)

DEST[15:0] ← SaturateToSignedWord (DEST[15:0] + SRC[15:0]);

(* Repeat add operation for 2nd through 7th words *)

DEST[127:112] ← SaturateToSignedWord (DEST[127:112] + SRC[127:112]);

VPADDSW (VEX.128 encoded version)

DEST[15:0]  SaturateToSignedWord (SRC1[15:0] + SRC2[15:0]);

(* Repeat subtract operation for 2nd through 7th words *)

DEST[127:112]  SaturateToSignedWord (SRC1[127:112] + SRC2[127:112]);

DEST[VLMAX-1:128]  0

VPADDSW (VEX.256 encoded version)

DEST[15:0]  SaturateToSignedWord (SRC1[15:0] + SRC2[15:0]);

(* Repeat add operation for 2nd through 15th words *)

DEST[255:240]  SaturateToSignedWord (SRC1[255:240] + SRC2[255:240])

PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation

Vol. 2B

4-45

INSTRUCTION SET REFERENCE, N-Z

PADDUSB/PADDUSW—Add Packed Unsigned Integers with Unsigned Saturation

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

0F DC /r¹

V/V

MMX

Add packed unsigned byte integers from

mm/m64 and mm and saturate the results.

PADDUSB mm, mm/m64

66 0F DC /r

V/V

SSE2

Add packed unsigned byte integers from

xmm2/m128 and xmm1 saturate the results.

PADDUSB xmm1, xmm2/m128

0F DD /r¹

V/V

MMX

Add packed unsigned word integers from

mm/m64 and mm and saturate the results.

PADDUSW mm, mm/m64

66 0F DD /r

V/V

SSE2

Add packed unsigned word integers from

xmm2/m128 to xmm1 and saturate the

PADDUSW xmm1, xmm2/m128

results.

VEX.NDS.128.660F.WIG DC /r

RVM

V/V

AVX

Add packed unsigned byte integers from

xmm3/m128 to xmm2 and saturate the

VPADDUSB xmm1, xmm2, xmm3/m128

results.

VEX.NDS.128.66.0F.WIG DD /r

RVM

V/V

AVX

Add packed unsigned word integers from

xmm3/m128 to xmm2 and saturate the

VPADDUSW xmm1, xmm2, xmm3/m128

results.

VEX.NDS.256.66.0F.WIG DC /r

RVM

V/V

AVX2

Add packed unsigned byte integers from

VPADDUSB ymm1, ymm2, ymm3/m256

ymm2, and ymm3/m256 and store the

saturated results in ymm1.

VEX.NDS.256.66.0F.WIG DD /r

RVM

V/V

AVX2

Add packed unsigned word integers from

VPADDUSW ymm1, ymm2, ymm3/m256

ymm2, and ymm3/m256 and store the

saturated results in ymm1.

NOTES:

1. See note in Section 2.4, “Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

Description

Performs a SIMD add of the packed unsigned integers from the source operand (second operand) and the destina-

tion operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD operation.

Overflow is handled with unsigned saturation, as described in the following paragraphs.

The (V)PADDUSB instruction adds packed unsigned byte integers. When an individual byte result is beyond the

range of an unsigned byte integer (that is, greater than FFH), the saturated value of FFH is written to the destina-

tion operand.

The (V)PADDUSW instruction adds packed unsigned word integers. When an individual word result is beyond the

range of an unsigned word integer (that is, greater than FFFFH), the saturated value of FFFFH is written to the

destination operand.

These instructions can operate on either 64-bit, 128-bit or 256-bit operands. When operating on 64-bit operands,

the destination operand must be an MMX technology register and the source operand can be either an MMX tech-

PADDUSB/PADDUSW—Add Packed Unsigned Integers with Unsigned Saturation

Vol. 2B

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INSTRUCTION SET REFERENCE, N-Z

nology register or a 64-bit memory location. In 64-bit mode, using a REX prefix in the form of REX.R permits this

instruction to access additional registers (XMM8-XMM15).

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation

PADDUSB (with 64-bit operands)

DEST[7:0] ← SaturateToUnsignedByte(DEST[7:0] + SRC (7:0] );

(* Repeat add operation for 2nd through 7th bytes *)

DEST[63:56] ← SaturateToUnsignedByte(DEST[63:56] + SRC[63:56]

PADDUSB (with 128-bit operands)

DEST[7:0] ← SaturateToUnsignedByte (DEST[7:0] + SRC[7:0]);

(* Repeat add operation for 2nd through 14th bytes *)

DEST[127:120] ← SaturateToUnSignedByte (DEST[127:120] + SRC[127:120]);

VPADDUSB (VEX.128 encoded version)

DEST[7:0]  SaturateToUnsignedByte (SRC1[7:0] + SRC2[7:0]);

(* Repeat subtract operation for 2nd through 14th bytes *)

DEST[127:120]  SaturateToUnsignedByte (SRC1[111:120] + SRC2[127:120]);

DEST[VLMAX-1:128]  0

VPADDUSB (VEX.256 encoded version)

DEST[7:0]  SaturateToUnsignedByte (SRC1[7:0] + SRC2[7:0]);

(* Repeat add operation for 2nd through 31st bytes *)

DEST[255:248] SaturateToUnsignedByte (SRC1[255:248] + SRC2[255:248]);

PADDUSW (with 64-bit operands)

DEST[15:0] ← SaturateToUnsignedWord(DEST[15:0] + SRC[15:0] );

(* Repeat add operation for 2nd and 3rd words *)

DEST[63:48] ← SaturateToUnsignedWord(DEST[63:48] + SRC[63:48] );

PADDUSW (with 128-bit operands)

DEST[15:0] ← SaturateToUnsignedWord (DEST[15:0] + SRC[15:0]);

(* Repeat add operation for 2nd through 7th words *)

DEST[127:112] ← SaturateToUnSignedWord (DEST[127:112] + SRC[127:112]);

VPADDUSW (VEX.128 encoded version)

DEST[15:0]  SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);

(* Repeat subtract operation for 2nd through 7th words *)

DEST[127:112]  SaturateToUnsignedWord (SRC1[127:112] + SRC2[127:112]);

DEST[VLMAX-1:128]  0

VPADDUSW (VEX.256 encoded version)

DEST[15:0]  SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);

(* Repeat add operation for 2nd through 15th words *)

DEST[255:240]  SaturateToUnsignedWord (SRC1[255:240] + SRC2[255:240])

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PADDUSB/PADDUSW—Add Packed Unsigned Integers with Unsigned Saturation

INSTRUCTION SET REFERENCE, N-Z

PALIGNR — Packed Align Right

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

0F 3A 0F /r ib¹

RMI V/V

SSSE3

Concatenate destination and source

operands, extract byte-aligned result shifted

PALIGNR mm1, mm2/m64, imm8

to the right by constant value in imm8 into

mm1.

66 0F 3A 0F /r ib

RMI V/V

SSSE3

Concatenate destination and source

operands, extract byte-aligned result shifted

PALIGNR xmm1, xmm2/m128, imm8

to the right by constant value in imm8 into

xmm1.

VEX.NDS.128.66.0F3A.WIG 0F /r ib

RVMI V/V

AVX

Concatenate xmm2 and xmm3/m128, extract

byte aligned result shifted to the right by

VPALIGNR xmm1, xmm2, xmm3/m128, imm8

constant value in imm8 and result is stored in

xmm1.

VEX.NDS.256.66.0F3A.WIG 0F /r ib

RVMI V/V

AVX2

Concatenate pairs of 16 bytes in ymm2 and

ymm3/m256 into 32-byte intermediate

VPALIGNR ymm1, ymm2, ymm3/m256, imm8

result, extract byte-aligned, 16-byte result

shifted to the right by constant values in

imm8 from each intermediate result, and two

16-byte results are stored in ymm1.

NOTES:

1. See note in Section 2.4, “Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RMI

ModRM:reg (r, w)

ModRM:r/m (r)

imm8

RVMI

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

(V)PALIGNR concatenates the destination operand (the first operand) and the source operand (the second

operand) into an intermediate composite, shifts the composite at byte granularity to the right by a constant imme-

diate, and extracts the right-aligned result into the destination. The first and the second operands can be an MMX,

XMM or a YMM register. The immediate value is considered unsigned. Immediate shift counts larger than the 2L

(i.e. 32 for 128-bit operands, or 16 for 64-bit operands) produce a zero result. Both operands can be MMX regis-

ters, XMM registers or YMM registers. When the source operand is a 128-bit memory operand, the operand must

be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.

In 64-bit mode, use the REX prefix to access additional registers.

128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain

unchanged.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register and contains two 16-byte blocks. The second

source operand is a YMM register or a 256-bit memory location containing two 16-byte block. The destination

operand is a YMM register and contain two 16-byte results. The imm8[7:0] is the common shift count used for the

two lower 16-byte block sources and the two upper 16-byte block sources. The low 16-byte block of the two source

4-50

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PALIGNR — Packed Align Right

INSTRUCTION SET REFERENCE, N-Z

operands produce the low 16-byte result of the destination operand, the high 16-byte block of the two source oper-

ands produce the high 16-byte result of the destination operand.

Concatenation is done with 128-bit data in the first and second source operand for both 128-bit and 256-bit

instructions. The high 128-bits of the intermediate composite 256-bit result came from the 128-bit data from the

first source operand; the low 128-bits of the intermediate result came from the 128-bit data of the second source

operand.

Note: VEX.L must be 0, otherwise the instruction will #UD.

127

SRC1

SRC2

Imm8[7:0]*8

255

128

255

128

SRC1

SRC2

Imm8[7:0]*8

255

128

127

DEST

Figure 4-3. 256-bit VPALIGN Instruction Operation

Operation

PALIGNR (with 64-bit operands)

temp1[127:0] = CONCATENATE(DEST,SRC)>>(imm8*8)

DEST[63:0] = temp1[63:0]

PALIGNR (with 128-bit operands)

temp1[255:0]  ((DEST[127:0] << 128) OR SRC[127:0])>>(imm8*8);

DEST[127:0]  temp1[127:0]

DEST[VLMAX-1:128] (Unmodified)

VPALIGNR (VEX.128 encoded version)

temp1[255:0]  ((SRC1[127:0] << 128) OR SRC2[127:0])>>(imm8*8);

DEST[127:0]  temp1[127:0]

DEST[VLMAX-1:128]  0

VPALIGNR (VEX.256 encoded version)

temp1[255:0]  ((SRC1[127:0] << 128) OR SRC2[127:0])>>(imm8[7:0]*8);

DEST[127:0]  temp1[127:0]

temp1[255:0]  ((SRC1[255:128] << 128) OR SRC2[255:128])>>(imm8[7:0]*8);

DEST[255:128]  temp1[127:0]

Intel C/C++ Compiler Intrinsic Equivalents

PALIGNR:

__m64 _mm_alignr_pi8 (__m64 a, __m64 b, int n)

(V)PALIGNR:

__m128i _mm_alignr_epi8 (__m128i a, __m128i b, int n)

VPALIGNR:

__m256i _mm256_alignr_epi8 (__m256i a, __m256i b, const int n)

PALIGNR — Packed Align Right

Vol. 2B

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INSTRUCTION SET REFERENCE, N-Z

PAND—Logical AND

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

0F DB /r¹

RM V/V

MMX

Bitwise AND mm/m64 and mm.

PAND mm, mm/m64

66 0F DB /r

RM V/V

SSE2

Bitwise AND of xmm2/m128 and xmm1.

PAND xmm1, xmm2/m128

VEX.NDS.128.66.0F.WIG DB /r

RVM V/V

AVX

Bitwise AND of xmm3/m128 and xmm.

VPAND xmm1, xmm2, xmm3/m128

VEX.NDS.256.66.0F.WIG DB /r

RVM V/V

AVX2

Bitwise AND of ymm2, and ymm3/m256 and

store result in ymm1.

VPAND ymm1, ymm2, ymm3/.m256

NOTES:

1. See note in Section 2.4, “Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

Description

Performs a bitwise logical AND operation on the first source operand and second source operand and stores the

result in the destination operand. Each bit of the result is set to 1 if the corresponding bits of the first and second

operands are 1, otherwise it is set to 0.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers

(XMM8-XMM15).

Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The

destination operand can be an MMX technology register.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation

PAND (128-bit Legacy SSE version)

DEST  DEST AND SRC

DEST[VLMAX-1:128] (Unmodified)

VPAND (VEX.128 encoded version)

DEST  SRC1 AND SRC2

DEST[VLMAX-1:128]  0

PAND—Logical AND

Vol. 2B

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INSTRUCTION SET REFERENCE, N-Z

PANDN—Logical AND NOT

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

0F DF /r¹

RM V/V

MMX

Bitwise AND NOT of mm/m64 and mm.

PANDN mm, mm/m64

66 0F DF /r

RM V/V

SSE2

Bitwise AND NOT of xmm2/m128 and xmm1.

PANDN xmm1, xmm2/m128

VEX.NDS.128.66.0F.WIG DF /r

RVM V/V

AVX

Bitwise AND NOT of xmm3/m128 and xmm2.

VPANDN xmm1, xmm2, xmm3/m128

VEX.NDS.256.66.0F.WIG DF /r

RVM V/V

AVX2

Bitwise AND NOT of ymm2, and ymm3/m256

and store result in ymm1.

VPANDN ymm1, ymm2, ymm3/m256

NOTES:

1. See note in Section 2.4, “Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

Description

Performs a bitwise logical NOT operation on the first source operand, then performs bitwise AND with second

source operand and stores the result in the destination operand. Each bit of the result is set to 1 if the corre-

sponding bit in the first operand is 0 and the corresponding bit in the second operand is 1, otherwise it is set to 0.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers

(XMM8-XMM15).

Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The

destination operand can be an MMX technology register.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation

PANDN(128-bit Legacy SSE version)

DEST  NOT(DEST) AND SRC

DEST[VLMAX-1:128] (Unmodified)

VPANDN (VEX.128 encoded version)

DEST  NOT(SRC1) AND SRC2

DEST[VLMAX-1:128]  0

PANDN—Logical AND NOT

Vol. 2B

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INSTRUCTION SET REFERENCE, N-Z

PAUSE—Spin Loop Hint

Opcode

Instruction

Op/

64-Bit

Compat/ Description

En Mode

Leg Mode

F3 90

PAUSE

NP Valid

Valid

Gives hint to processor that improves

performance of spin-wait loops.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

Description

Improves the performance of spin-wait loops. When executing a “spin-wait loop,” processors will suffer a severe

performance penalty when exiting the loop because it detects a possible memory order violation. The PAUSE

instruction provides a hint to the processor that the code sequence is a spin-wait loop. The processor uses this hint

to avoid the memory order violation in most situations, which greatly improves processor performance. For this

reason, it is recommended that a PAUSE instruction be placed in all spin-wait loops.

An additional function of the PAUSE instruction is to reduce the power consumed by a processor while executing a

spin loop. A processor can execute a spin-wait loop extremely quickly, causing the processor to consume a lot of

power while it waits for the resource it is spinning on to become available. Inserting a pause instruction in a spin-

wait loop greatly reduces the processor’s power consumption.

This instruction was introduced in the Pentium 4 processors, but is backward compatible with all IA-32 processors.

In earlier IA-32 processors, the PAUSE instruction operates like a NOP instruction. The Pentium 4 and Intel Xeon

processors implement the PAUSE instruction as a delay. The delay is finite and can be zero for some processors.

This instruction does not change the architectural state of the processor (that is, it performs essentially a delaying

no-op operation).

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

Execute_Next_Instruction(DELAY);

Numeric Exceptions

None.

Exceptions (All Operating Modes)

#UD

If the LOCK prefix is used.

PAUSE—Spin Loop Hint

Vol. 2B

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INSTRUCTION SET REFERENCE, N-Z

PAVGB/PAVGW—Average Packed Integers

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

0F E0 /r¹

RM V/V

SSE

Average packed unsigned byte integers from

mm2/m64 and mm1 with rounding.

PAVGB mm1, mm2/m64

66 0F E0, /r

RM V/V

SSE2

Average packed unsigned byte integers from

xmm2/m128 and xmm1 with rounding.

PAVGB xmm1, xmm2/m128

0F E3 /r¹

RM V/V

SSE

Average packed unsigned word integers from

mm2/m64 and mm1 with rounding.

PAVGW mm1, mm2/m64

66 0F E3 /r

RM V/V

SSE2

Average packed unsigned word integers from

xmm2/m128 and xmm1 with rounding.

PAVGW xmm1, xmm2/m128

VEX.NDS.128.66.0F.WIG E0 /r

RVM V/V

AVX

Average packed unsigned byte integers from

xmm3/m128 and xmm2 with rounding.

VPAVGB xmm1, xmm2, xmm3/m128

VEX.NDS.128.66.0F.WIG E3 /r

RVM V/V

AVX

Average packed unsigned word integers from

xmm3/m128 and xmm2 with rounding.

VPAVGW xmm1, xmm2, xmm3/m128

VEX.NDS.256.66.0F.WIG E0 /r

RVM V/V

AVX2

Average packed unsigned byte integers from

ymm2, and ymm3/m256 with rounding and

VPAVGB ymm1, ymm2, ymm3/m256

store to ymm1.

VEX.NDS.256.66.0F.WIG E3 /r

RVM V/V

AVX2

Average packed unsigned word integers from

VPAVGW ymm1, ymm2, ymm3/m256

ymm2, ymm3/m256 with rounding to ymm1.

NOTES:

1. See note in Section 2.4, “Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

Description

Performs a SIMD average of the packed unsigned integers from the source operand (second operand) and the

destination operand (first operand), and stores the results in the destination operand. For each corresponding pair

of data elements in the first and second operands, the elements are added together, a 1 is added to the temporary

sum, and that result is shifted right one bit position.

The (V)PAVGB instruction operates on packed unsigned bytes and the (V)PAVGW instruction operates on packed

unsigned words.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers

(XMM8-XMM15).

Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The

destination operand can be an MMX technology register.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.

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INSTRUCTION SET REFERENCE, N-Z

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

Operation

PAVGB (with 64-bit operands)

DEST[7:0] ← (SRC[7:0] + DEST[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)

(* Repeat operation performed for bytes 2 through 6 *)

DEST[63:56] ← (SRC[63:56] + DEST[63:56] + 1) >> 1;

PAVGW (with 64-bit operands)

DEST[15:0] ← (SRC[15:0] + DEST[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)

(* Repeat operation performed for words 2 and 3 *)

DEST[63:48] ← (SRC[63:48] + DEST[63:48] + 1) >> 1;

PAVGB (with 128-bit operands)

DEST[7:0] ← (SRC[7:0] + DEST[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)

(* Repeat operation performed for bytes 2 through 14 *)

DEST[127:120] ← (SRC[127:120] + DEST[127:120] + 1) >> 1;

PAVGW (with 128-bit operands)

DEST[15:0] ← (SRC[15:0] + DEST[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)

(* Repeat operation performed for words 2 through 6 *)

DEST[127:112] ← (SRC[127:112] + DEST[127:112] + 1) >> 1;

VPAVGB (VEX.128 encoded version)

DEST[7:0]  (SRC1[7:0] + SRC2[7:0] + 1) >> 1;

(* Repeat operation performed for bytes 2 through 15 *)

DEST[127:120]  (SRC1[127:120] + SRC2[127:120] + 1) >> 1

DEST[VLMAX-1:128]  0

VPAVGW (VEX.128 encoded version)

DEST[15:0]  (SRC1[15:0] + SRC2[15:0] + 1) >> 1;

(* Repeat operation performed for 16-bit words 2 through 7 *)

DEST[127:112]  (SRC1[127:112] + SRC2[127:112] + 1) >> 1

DEST[VLMAX-1:128]  0

VPAVGB (VEX.256 encoded instruction)

DEST[7:0]  (SRC1[7:0] + SRC2[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)

(* Repeat operation performed for bytes 2 through 31)

DEST[255:248]  (SRC1[255:248] + SRC2[255:248] + 1) >> 1;

VPAVGW (VEX.256 encoded instruction)

DEST[15:0]  (SRC1[15:0] + SRC2[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)

(* Repeat operation performed for words 2 through 15)

DEST[255:14])  (SRC1[255:240] + SRC2[255:240] + 1) >> 1;

Intel C/C++ Compiler Intrinsic Equivalent

PAVGB:

__m64 _mm_avg_pu8 (__m64 a, __m64 b)

PAVGW:

__m64 _mm_avg_pu16 (__m64 a, __m64 b)

(V)PAVGB:

__m128i _mm_avg_epu8 ( __m128i a, __m128i b)

PAVGB/PAVGW—Average Packed Integers

Vol. 2B

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INSTRUCTION SET REFERENCE, N-Z

PBLENDVB — Variable Blend Packed Bytes

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

Mode

Feature

Support Flag

66 0F 38 10 /r

RM V/V

SSE4_1

Select byte values from xmm1 and

PBLENDVB xmm1, xmm2/m128, <XMM0>

xmm2/m128 from mask specified in the high

bit of each byte in XMM0 and store the

values into xmm1.

VEX.NDS.128.66.0F3A.W0 4C /r /is4

RVMR V/V

AVX

Select byte values from xmm2 and

VPBLENDVB xmm1, xmm2, xmm3/m128, xmm4

xmm3/m128 using mask bits in the specified

mask register, xmm4, and store the values

into xmm1.

VEX.NDS.256.66.0F3A.W0 4C /r /is4

RVMR V/V

AVX2

Select byte values from ymm2 and

VPBLENDVB ymm1, ymm2, ymm3/m256, ymm4

ymm3/m256 from mask specified in the high

bit of each byte in ymm4 and store the

values into ymm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

<XMM0>

RVMR

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8[7:4]

Description

Conditionally copies byte elements from the source operand (second operand) to the destination operand (first

operand) depending on mask bits defined in the implicit third register argument, XMM0. The mask bits are the

most significant bit in each byte element of the XMM0 register.

If a mask bit is “1", then the corresponding byte element in the source operand is copied to the destination, else

the byte element in the destination operand is left unchanged.

The register assignment of the implicit third operand is defined to be the architectural register XMM0.

128-bit Legacy SSE version: The first source operand and the destination operand is the same. Bits (VLMAX-1:128)

of the corresponding YMM destination register remain unchanged. The mask register operand is implicitly defined

to be the architectural register XMM0. An attempt to execute PBLENDVB with a VEX prefix will cause #UD.

VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second

source operand is an XMM register or 128-bit memory location. The mask operand is the third source register, and

encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is

ignored. The upper bits (VLMAX-1:128) of the corresponding YMM register (destination register) are zeroed. VEX.L

must be 0, otherwise the instruction will #UD. VEX.W must be 0, otherwise, the instruction will #UD.

VEX.256 encoded version: The first source operand and the destination operand are YMM registers. The second

source operand is an YMM register or 256-bit memory location. The third source register is an YMM register and

encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is

ignored.

VPBLENDVB permits the mask to be any XMM or YMM register. In contrast, PBLENDVB treats XMM0 implicitly as the

mask and do not support non-destructive destination operation. An attempt to execute PBLENDVB encoded with a

VEX prefix will cause a #UD exception.

Operation

PBLENDVB (128-bit Legacy SSE version)

MASK  XMM0

IF (MASK[7] = 1) THEN DEST[7:0]  SRC[7:0];

ELSE DEST[7:0]  DEST[7:0];

IF (MASK[15] = 1) THEN DEST[15:8]  SRC[15:8];

PBLENDVB — Variable Blend Packed Bytes

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INSTRUCTION SET REFERENCE, N-Z

ELSE DEST[15:8]  DEST[15:8];

IF (MASK[23] = 1) THEN DEST[23:16]  SRC[23:16]

ELSE DEST[23:16]  DEST[23:16];

IF (MASK[31] = 1) THEN DEST[31:24]  SRC[31:24]

ELSE DEST[31:24]  DEST[31:24];

IF (MASK[39] = 1) THEN DEST[39:32]  SRC[39:32]

ELSE DEST[39:32]  DEST[39:32];

IF (MASK[47] = 1) THEN DEST[47:40]  SRC[47:40]

ELSE DEST[47:40]  DEST[47:40];

IF (MASK[55] = 1) THEN DEST[55:48]  SRC[55:48]

ELSE DEST[55:48]  DEST[55:48];

IF (MASK[63] = 1) THEN DEST[63:56]  SRC[63:56]

ELSE DEST[63:56]  DEST[63:56];

IF (MASK[71] = 1) THEN DEST[71:64]  SRC[71:64]

ELSE DEST[71:64]  DEST[71:64];

IF (MASK[79] = 1) THEN DEST[79:72]  SRC[79:72]

ELSE DEST[79:72]  DEST[79:72];

IF (MASK[87] = 1) THEN DEST[87:80]  SRC[87:80]

ELSE DEST[87:80]  DEST[87:80];

IF (MASK[95] = 1) THEN DEST[95:88]  SRC[95:88]

ELSE DEST[95:88] DEST[95:88];

IF (MASK[103] = 1) THEN DEST[103:96]  SRC[103:96]

ELSE DEST[103:96] DEST[103:96];

IF (MASK[111] = 1) THEN DEST[111:104]  SRC[111:104]

ELSE DEST[111:104]  DEST[111:104];

IF (MASK[119] = 1) THEN DEST[119:112]  SRC[119:112]

ELSE DEST[119:112]  DEST[119:112];

IF (MASK[127] = 1) THEN DEST[127:120]  SRC[127:120]

ELSE DEST[127:120]  DEST[127:120])

DEST[VLMAX-1:128] (Unmodified)

VPBLENDVB (VEX.128 encoded version)

MASK  SRC3

IF (MASK[7] = 1) THEN DEST[7:0]  SRC2[7:0];

ELSE DEST[7:0]  SRC1[7:0];

IF (MASK[15] = 1) THEN DEST[15:8]  SRC2[15:8];

ELSE DEST[15:8]  SRC1[15:8];

IF (MASK[23] = 1) THEN DEST[23:16]  SRC2[23:16]

ELSE DEST[23:16]  SRC1[23:16];

IF (MASK[31] = 1) THEN DEST[31:24]  SRC2[31:24]

ELSE DEST[31:24]  SRC1[31:24];

IF (MASK[39] = 1) THEN DEST[39:32]  SRC2[39:32]

ELSE DEST[39:32]  SRC1[39:32];

IF (MASK[47] = 1) THEN DEST[47:40]  SRC2[47:40]

ELSE DEST[47:40]  SRC1[47:40];

IF (MASK[55] = 1) THEN DEST[55:48]  SRC2[55:48]

ELSE DEST[55:48]  SRC1[55:48];

IF (MASK[63] = 1) THEN DEST[63:56]  SRC2[63:56]

ELSE DEST[63:56]  SRC1[63:56];

IF (MASK[71] = 1) THEN DEST[71:64]  SRC2[71:64]

ELSE DEST[71:64]  SRC1[71:64];

IF (MASK[79] = 1) THEN DEST[79:72]  SRC2[79:72]

ELSE DEST[79:72]  SRC1[79:72];

IF (MASK[87] = 1) THEN DEST[87:80]  SRC2[87:80]

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PBLENDVB — Variable Blend Packed Bytes

INSTRUCTION SET REFERENCE, N-Z

ELSE DEST[87:80]  SRC1[87:80];

IF (MASK[95] = 1) THEN DEST[95:88]  SRC2[95:88]

ELSE DEST[95:88] SRC1[95:88];

IF (MASK[103] = 1) THEN DEST[103:96]  SRC2[103:96]

ELSE DEST[103:96] SRC1[103:96];

IF (MASK[111] = 1) THEN DEST[111:104]  SRC2[111:104]

ELSE DEST[111:104]  SRC1[111:104];

IF (MASK[119] = 1) THEN DEST[119:112]  SRC2[119:112]

ELSE DEST[119:112]  SRC1[119:112];

IF (MASK[127] = 1) THEN DEST[127:120]  SRC2[127:120]

ELSE DEST[127:120]  SRC1[127:120])

DEST[VLMAX-1:128]  0

VPBLENDVB (VEX.256 encoded version)

MASK  SRC3

IF (MASK[7] == 1) THEN DEST[7:0]  SRC2[7:0];

ELSE DEST[7:0]  SRC1[7:0];

IF (MASK[15] == 1) THEN DEST[15:8] SRC2[15:8];

ELSE DEST[15:8]  SRC1[15:8];

IF (MASK[23] == 1) THEN DEST[23:16] SRC2[23:16]

ELSE DEST[23:16]  SRC1[23:16];

IF (MASK[31] == 1) THEN DEST[31:24]  SRC2[31:24]

ELSE DEST[31:24]  SRC1[31:24];

IF (MASK[39] == 1) THEN DEST[39:32]  SRC2[39:32]

ELSE DEST[39:32]  SRC1[39:32];

IF (MASK[47] == 1) THEN DEST[47:40]  SRC2[47:40]

ELSE DEST[47:40]  SRC1[47:40];

IF (MASK[55] == 1) THEN DEST[55:48]  SRC2[55:48]

ELSE DEST[55:48]  SRC1[55:48];

IF (MASK[63] == 1) THEN DEST[63:56] SRC2[63:56]

ELSE DEST[63:56]  SRC1[63:56];

IF (MASK[71] == 1) THEN DEST[71:64] SRC2[71:64]

ELSE DEST[71:64]  SRC1[71:64];

IF (MASK[79] == 1) THEN DEST[79:72]  SRC2[79:72]

ELSE DEST[79:72]  SRC1[79:72];

IF (MASK[87] == 1) THEN DEST[87:80]  SRC2[87:80]

ELSE DEST[87:80]  SRC1[87:80];

IF (MASK[95] == 1) THEN DEST[95:88]  SRC2[95:88]

ELSE DEST[95:88]  SRC1[95:88];

IF (MASK[103] == 1) THEN DEST[103:96]  SRC2[103:96]

ELSE DEST[103:96]  SRC1[103:96];

IF (MASK[111] == 1) THEN DEST[111:104]  SRC2[111:104]

ELSE DEST[111:104]  SRC1[111:104];

IF (MASK[119] == 1) THEN DEST[119:112]  SRC2[119:112]

ELSE DEST[119:112]  SRC1[119:112];

IF (MASK[127] == 1) THEN DEST[127:120]  SRC2[127:120]

ELSE DEST[127:120]  SRC1[127:120])

IF (MASK[135] == 1) THEN DEST[135:128]  SRC2[135:128];

ELSE DEST[135:128]  SRC1[135:128];

IF (MASK[143] == 1) THEN DEST[143:136]  SRC2[143:136];

ELSE DEST[[143:136]  SRC1[143:136];

IF (MASK[151] == 1) THEN DEST[151:144]  SRC2[151:144]

ELSE DEST[151:144]  SRC1[151:144];

IF (MASK[159] == 1) THEN DEST[159:152]  SRC2[159:152]

PBLENDVB — Variable Blend Packed Bytes

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INSTRUCTION SET REFERENCE, N-Z

ELSE DEST[159:152]  SRC1[159:152];

IF (MASK[167] == 1) THEN DEST[167:160]  SRC2[167:160]

ELSE DEST[167:160]  SRC1[167:160];

IF (MASK[175] == 1) THEN DEST[175:168]  SRC2[175:168]

ELSE DEST[175:168]  SRC1[175:168];

IF (MASK[183] == 1) THEN DEST[183:176]  SRC2[183:176]

ELSE DEST[183:176]  SRC1[183:176];

IF (MASK[191] == 1) THEN DEST[191:184]  SRC2[191:184]

ELSE DEST[191:184]  SRC1[191:184];

IF (MASK[199] == 1) THEN DEST[199:192]  SRC2[199:192]

ELSE DEST[199:192]  SRC1[199:192];

IF (MASK[207] == 1) THEN DEST[207:200]  SRC2[207:200]

ELSE DEST[207:200]  SRC1[207:200]

IF (MASK[215] == 1) THEN DEST[215:208]  SRC2[215:208]

ELSE DEST[215:208]  SRC1[215:208];

IF (MASK[223] == 1) THEN DEST[223:216]  SRC2[223:216]

ELSE DEST[223:216]  SRC1[223:216];

IF (MASK[231] == 1) THEN DEST[231:224]  SRC2[231:224]

ELSE DEST[231:224]  SRC1[231:224];

IF (MASK[239] == 1) THEN DEST[239:232]  SRC2[239:232]

ELSE DEST[239:232]  SRC1[239:232];

IF (MASK[247] == 1) THEN DEST[247:240]  SRC2[247:240]

ELSE DEST[247:240]  SRC1[247:240];

IF (MASK[255] == 1) THEN DEST[255:248]  SRC2[255:248]

ELSE DEST[255:248]  SRC1[255:248]

Intel C/C++ Compiler Intrinsic Equivalent

(V)PBLENDVB:

__m128i _mm_blendv_epi8 (__m128i v1, __m128i v2, __m128i mask);

VPBLENDVB:

__m256i _mm256_blendv_epi8 (__m256i v1, __m256i v2, __m256i mask);

Flags Affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Exceptions Type 4; additionally

#UD

If VEX.L = 1.

If VEX.W = 1.

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PBLENDVB — Variable Blend Packed Bytes

INSTRUCTION SET REFERENCE, N-Z

PBLENDW — Blend Packed Words

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

66 0F 3A 0E /r ib

RMI V/V

SSE4_1

Select words from xmm1 and xmm2/m128

PBLENDW xmm1, xmm2/m128, imm8

from mask specified in imm8 and store the

values into xmm1.

VEX.NDS.128.66.0F3A.WIG 0E /r ib

RVMI V/V

AVX

Select words from xmm2 and xmm3/m128

VPBLENDW xmm1, xmm2, xmm3/m128, imm8

from mask specified in imm8 and store the

values into xmm1.

VEX.NDS.256.66.0F3A.WIG 0E /r ib

RVMI V/V

AVX2

Select words from ymm2 and ymm3/m256

VPBLENDW ymm1, ymm2, ymm3/m256, imm8

from mask specified in imm8 and store the

values into ymm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RMI

ModRM:reg (r, w)

ModRM:r/m (r)

imm8

RVMI

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Words from the source operand (second operand) are conditionally written to the destination operand (first

operand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a mask

that determines whether the corresponding word in the destination is copied from the source. If a bit in the mask,

corresponding to a word, is “1", then the word is copied, else the word element in the destination operand is

unchanged.

128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The

first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination

VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The

first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register

are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

Operation

PBLENDW (128-bit Legacy SSE version)

IF (imm8[0] = 1) THEN DEST[15:0]  SRC[15:0]

ELSE DEST[15:0]  DEST[15:0]

IF (imm8[1] = 1) THEN DEST[31:16]  SRC[31:16]

ELSE DEST[31:16]  DEST[31:16]

IF (imm8[2] = 1) THEN DEST[47:32]  SRC[47:32]

ELSE DEST[47:32]  DEST[47:32]

IF (imm8[3] = 1) THEN DEST[63:48]  SRC[63:48]

ELSE DEST[63:48]  DEST[63:48]

IF (imm8[4] = 1) THEN DEST[79:64]  SRC[79:64]

ELSE DEST[79:64]  DEST[79:64]

IF (imm8[5] = 1) THEN DEST[95:80]  SRC[95:80]

ELSE DEST[95:80]  DEST[95:80]

IF (imm8[6] = 1) THEN DEST[111:96]  SRC[111:96]

ELSE DEST[111:96]  DEST[111:96]

IF (imm8[7] = 1) THEN DEST[127:112]  SRC[127:112]

PBLENDW — Blend Packed Words

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INSTRUCTION SET REFERENCE, N-Z

ELSE DEST[127:112]  DEST[127:112]

VPBLENDW (VEX.128 encoded version)

IF (imm8[0] = 1) THEN DEST[15:0]  SRC2[15:0]

ELSE DEST[15:0]  SRC1[15:0]

IF (imm8[1] = 1) THEN DEST[31:16]  SRC2[31:16]

ELSE DEST[31:16]  SRC1[31:16]

IF (imm8[2] = 1) THEN DEST[47:32]  SRC2[47:32]

ELSE DEST[47:32]  SRC1[47:32]

IF (imm8[3] = 1) THEN DEST[63:48]  SRC2[63:48]

ELSE DEST[63:48]  SRC1[63:48]

IF (imm8[4] = 1) THEN DEST[79:64]  SRC2[79:64]

ELSE DEST[79:64]  SRC1[79:64]

IF (imm8[5] = 1) THEN DEST[95:80]  SRC2[95:80]

ELSE DEST[95:80]  SRC1[95:80]

IF (imm8[6] = 1) THEN DEST[111:96]  SRC2[111:96]

ELSE DEST[111:96]  SRC1[111:96]

IF (imm8[7] = 1) THEN DEST[127:112]  SRC2[127:112]

ELSE DEST[127:112]  SRC1[127:112]

DEST[VLMAX-1:128]  0

VPBLENDW (VEX.256 encoded version)

IF (imm8[0] == 1) THEN DEST[15:0]  SRC2[15:0]

ELSE DEST[15:0]  SRC1[15:0]

IF (imm8[1] == 1) THEN DEST[31:16]  SRC2[31:16]

ELSE DEST[31:16]  SRC1[31:16]

IF (imm8[2] == 1) THEN DEST[47:32]  SRC2[47:32]

ELSE DEST[47:32]  SRC1[47:32]

IF (imm8[3] == 1) THEN DEST[63:48]  SRC2[63:48]

ELSE DEST[63:48]  SRC1[63:48]

IF (imm8[4] == 1) THEN DEST[79:64]  SRC2[79:64]

ELSE DEST[79:64]  SRC1[79:64]

IF (imm8[5] == 1) THEN DEST[95:80]  SRC2[95:80]

ELSE DEST[95:80]  SRC1[95:80]

IF (imm8[6] == 1) THEN DEST[111:96]  SRC2[111:96]

ELSE DEST[111:96]  SRC1[111:96]

IF (imm8[7] == 1) THEN DEST[127:112]  SRC2[127:112]

ELSE DEST[127:112]  SRC1[127:112]

IF (imm8[0] == 1) THEN DEST[143:128]  SRC2[143:128]

ELSE DEST[143:128]  SRC1[143:128]

IF (imm8[1] == 1) THEN DEST[159:144]  SRC2[159:144]

ELSE DEST[159:144]  SRC1[159:144]

IF (imm8[2] == 1) THEN DEST[175:160]  SRC2[175:160]

ELSE DEST[175:160]  SRC1[175:160]

IF (imm8[3] == 1) THEN DEST[191:176]  SRC2[191:176]

ELSE DEST[191:176]  SRC1[191:176]

IF (imm8[4] == 1) THEN DEST[207:192]  SRC2[207:192]

ELSE DEST[207:192]  SRC1[207:192]

IF (imm8[5] == 1) THEN DEST[223:208]  SRC2[223:208]

ELSE DEST[223:208]  SRC1[223:208]

IF (imm8[6] == 1) THEN DEST[239:224]  SRC2[239:224]

ELSE DEST[239:224]  SRC1[239:224]

IF (imm8[7] == 1) THEN DEST[255:240]  SRC2[255:240]

ELSE DEST[255:240]  SRC1[255:240]

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PBLENDW — Blend Packed Words

INSTRUCTION SET REFERENCE, N-Z

PCLMULQDQ - Carry-Less Multiplication Quadword

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

66 0F 3A 44 /r ib

RMI V/V

CLMUL

Carry-less multiplication of one quadword of

PCLMULQDQ xmm1, xmm2/m128, imm8

xmm1 by one quadword of xmm2/m128,

stores the 128-bit result in xmm1. The imme-

diate is used to determine which quadwords

of xmm1 and xmm2/m128 should be used.

VEX.NDS.128.66.0F3A.WIG 44 /r ib

RVMI V/V

Both

Carry-less multiplication of one quadword of

VPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8

CLMUL

xmm2 by one quadword of xmm3/m128,

and AVX

stores the 128-bit result in xmm1. The imme-

flags

diate is used to determine which quadwords

of xmm2 and xmm3/m128 should be used.

Instruction Operand Encoding

Op/En

Operand 1

Operand2

Operand3

Operand4

RMI

ModRM:reg (r, w)

ModRM:r/m (r)

imm8

RVMI

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Performs a carry-less multiplication of two quadwords, selected from the first source and second source operand

according to the value of the immediate byte. Bits 4 and 0 are used to select which 64-bit half of each operand to

use according to Table 4-10, other bits of the immediate byte are ignored.

Table 4-10. PCLMULQDQ Quadword Selection of Immediate Byte

Imm[4]

Imm[0]

PCLMULQDQ Operation

CL_MUL( SRC2¹[63:0], SRC1[63:0] )

CL_MUL( SRC2[63:0], SRC1[127:64] )

CL_MUL( SRC2[127:64], SRC1[63:0] )

CL_MUL( SRC2[127:64], SRC1[127:64] )

NOTES:

1. SRC2 denotes the second source operand, which can be a register or memory; SRC1 denotes the first source and destination oper-

and.

The first source operand and the destination operand are the same and must be an XMM register. The second

source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding

YMM destination register remain unchanged.

Compilers and assemblers may implement the following pseudo-op syntax to simply programming and emit the

required encoding for Imm8.

Table 4-11. Pseudo-Op and PCLMULQDQ Implementation

Pseudo-Op

Imm8 Encoding

PCLMULLQLQDQ xmm1, xmm2

0000_0000B

PCLMULHQLQDQ xmm1, xmm2

0000_0001B

PCLMULLQHDQ xmm1, xmm2

0001_0000B

PCLMULHQHDQ xmm1, xmm2

0001_0001B

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PCLMULQDQ - Carry-Less Multiplication Quadword

INSTRUCTION SET REFERENCE, N-Z

Operation

PCLMULQDQ

IF (Imm8[0] = 0 )

THEN

TEMP1  SRC1 [63:0];

ELSE

TEMP1  SRC1 [127:64];

IF (Imm8[4] = 0 )

THEN

TEMP2  SRC2 [63:0];

ELSE

TEMP2  SRC2 [127:64];

For i = 0 to 63 {

TmpB [ i ]  (TEMP1[ 0 ] and TEMP2[ i ]);

For j = 1 to i {

TmpB [ i ]  TmpB [ i ] xor (TEMP1[ j ] and TEMP2[ i - j ])

}

DEST[ i ]  TmpB[ i ];

}

For i = 64 to 126 {

TmpB [ i ]  0;

For j = i - 63 to 63 {

TmpB [ i ]  TmpB [ i ] xor (TEMP1[ j ] and TEMP2[ i - j ])

}

DEST[ i ]  TmpB[ i ];

}

DEST[127]  0;

DEST[VLMAX-1:128] (Unmodified)

VPCLMULQDQ

IF (Imm8[0] = 0 )

THEN

TEMP1  SRC1 [63:0];

ELSE

TEMP1  SRC1 [127:64];

IF (Imm8[4] = 0 )

THEN

TEMP2  SRC2 [63:0];

ELSE

TEMP2  SRC2 [127:64];

For i = 0 to 63 {

TmpB [ i ]  (TEMP1[ 0 ] and TEMP2[ i ]);

For j = 1 to i {

TmpB [i]  TmpB [i] xor (TEMP1[ j ] and TEMP2[ i - j ])

}

DEST[i]  TmpB[i];

}

For i = 64 to 126 {

TmpB [ i ]  0;

For j = i - 63 to 63 {

PCLMULQDQ - Carry-Less Multiplication Quadword

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INSTRUCTION SET REFERENCE, N-Z

PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

0F 74 /r¹

V/V

MMX

Compare packed bytes in mm/m64 and mm

for equality.

PCMPEQB mm, mm/m64

66 0F 74 /r

V/V

SSE2

Compare packed bytes in xmm2/m128 and

xmm1 for equality.

PCMPEQB xmm1, xmm2/m128

0F 75 /r¹

V/V

MMX

Compare packed words in mm/m64 and mm

for equality.

PCMPEQW mm, mm/m64

66 0F 75 /r

V/V

SSE2

Compare packed words in xmm2/m128 and

xmm1 for equality.

PCMPEQW xmm1, xmm2/m128

0F 76 /r¹

V/V

MMX

Compare packed doublewords in mm/m64 and

mm for equality.

PCMPEQD mm, mm/m64

66 0F 76 /r

V/V

SSE2

Compare packed doublewords in xmm2/m128

and xmm1 for equality.

PCMPEQD xmm1, xmm2/m128

VEX.NDS.128.66.0F.WIG 74 /r

RVM

V/V

AVX

Compare packed bytes in xmm3/m128 and

xmm2 for equality.

VPCMPEQB xmm1, xmm2, xmm3/m128

VEX.NDS.128.66.0F.WIG 75 /r

RVM

V/V

AVX

Compare packed words in xmm3/m128 and

xmm2 for equality.

VPCMPEQW xmm1, xmm2, xmm3/m128

VEX.NDS.128.66.0F.WIG 76 /r

RVM

V/V

AVX

Compare packed doublewords in xmm3/m128

and xmm2 for equality.

VPCMPEQD xmm1, xmm2, xmm3/m128

VEX.NDS.256.66.0F.WIG 75 /r

RVM

V/V

AVX2

Compare packed words in ymm3/m256 and

ymm2 for equality.

VPCMPEQW ymm1, ymm2, ymm3 /m256

VEX.NDS.256.66.0F.WIG 76 /r

RVM

V/V

AVX2

Compare packed doublewords in ymm3/m256

and ymm2 for equality.

VPCMPEQD ymm1, ymm2, ymm3 /m256

VEX.NDS.256.66.0F38.WIG 29 /r

RVM

V/V

AVX2

Compare packed quadwords in ymm3/m256

and ymm2 for equality.

VPCMPEQQ ymm1, ymm2, ymm3 /m256

NOTES:

1. See note in Section 2.4, “Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

Description

Performs a SIMD compare for equality of the packed bytes, words, or doublewords in the destination operand (first

operand) and the source operand (second operand). If a pair of data elements is equal, the corresponding data

element in the destination operand is set to all 1s; otherwise, it is set to all 0s.

The (V)PCMPEQB instruction compares the corresponding bytes in the destination and source operands; the

(V)PCMPEQW instruction compares the corresponding words in the destination and source operands; and the

(V)PCMPEQD instruction compares the corresponding doublewords in the destination and source operands.

PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal

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INSTRUCTION SET REFERENCE, N-Z

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers

(XMM8-XMM15).

Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The

destination operand can be an MMX technology register.

128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The

first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination

VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The

first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register

are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation

PCMPEQB (with 64-bit operands)

IF DEST[7:0] = SRC[7:0]

THEN DEST[7:0) ← FFH;

ELSE DEST[7:0] ← 0; FI;

(* Continue comparison of 2nd through 7th bytes in DEST and SRC *)

IF DEST[63:56] = SRC[63:56]

THEN DEST[63:56] ← FFH;

ELSE DEST[63:56] ← 0; FI;

PCMPEQB (with 128-bit operands)

IF DEST[7:0] = SRC[7:0]

THEN DEST[7:0) ← FFH;

ELSE DEST[7:0] ← 0; FI;

(* Continue comparison of 2nd through 15th bytes in DEST and SRC *)

IF DEST[127:120] = SRC[127:120]

THEN DEST[127:120] ← FFH;

ELSE DEST[127:120] ← 0; FI;

VPCMPEQB (VEX.128 encoded version)

DEST[127:0] COMPARE_BYTES_EQUAL(SRC1[127:0],SRC2[127:0])

DEST[VLMAX-1:128]  0

VPCMPEQB (VEX.256 encoded version)

DEST[127:0] COMPARE_BYTES_EQUAL(SRC1[127:0],SRC2[127:0])

DEST[255:128] COMPARE_BYTES_EQUAL(SRC1[255:128],SRC2[255:128])

PCMPEQW (with 64-bit operands)

IF DEST[15:0] = SRC[15:0]

THEN DEST[15:0] ← FFFFH;

ELSE DEST[15:0] ← 0; FI;

(* Continue comparison of 2nd and 3rd words in DEST and SRC *)

IF DEST[63:48] = SRC[63:48]

THEN DEST[63:48] ← FFFFH;

ELSE DEST[63:48] ← 0; FI;

PCMPEQW (with 128-bit operands)

IF DEST[15:0] = SRC[15:0]

THEN DEST[15:0] ← FFFFH;

ELSE DEST[15:0] ← 0; FI;

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PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal

INSTRUCTION SET REFERENCE, N-Z

(* Continue comparison of 2nd through 7th words in DEST and SRC *)

IF DEST[127:112] = SRC[127:112]

THEN DEST[127:112] ← FFFFH;

ELSE DEST[127:112] ← 0; FI;

VPCMPEQW (VEX.128 encoded version)

DEST[127:0] COMPARE_WORDS_EQUAL(SRC1[127:0],SRC2[127:0])

DEST[VLMAX-1:128]  0

VPCMPEQW (VEX.256 encoded version)

DEST[127:0] COMPARE_WORDS_EQUAL(SRC1[127:0],SRC2[127:0])

DEST[255:128] COMPARE_WORDS_EQUAL(SRC1[255:128],SRC2[255:128])

PCMPEQD (with 64-bit operands)

IF DEST[31:0] = SRC[31:0]

THEN DEST[31:0] ← FFFFFFFFH;

ELSE DEST[31:0] ← 0; FI;

IF DEST[63:32] = SRC[63:32]

THEN DEST[63:32] ← FFFFFFFFH;

ELSE DEST[63:32] ← 0; FI;

PCMPEQD (with 128-bit operands)

IF DEST[31:0] = SRC[31:0]

THEN DEST[31:0] ← FFFFFFFFH;

ELSE DEST[31:0] ← 0; FI;

(* Continue comparison of 2nd and 3rd doublewords in DEST and SRC *)

IF DEST[127:96] = SRC[127:96]

THEN DEST[127:96] ← FFFFFFFFH;

ELSE DEST[127:96] ← 0; FI;

VPCMPEQD (VEX.128 encoded version)

DEST[127:0] COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])

DEST[VLMAX-1:128]  0

VPCMPEQD (VEX.256 encoded version)

DEST[127:0] COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])

DEST[255:128] COMPARE_DWORDS_EQUAL(SRC1[255:128],SRC2[255:128])

Intel C/C++ Compiler Intrinsic Equivalents

PCMPEQB:

__m64 _mm_cmpeq_pi8 (__m64 m1, __m64 m2)

PCMPEQW:

__m64 _mm_cmpeq_pi16 (__m64 m1, __m64 m2)

PCMPEQD:

__m64 _mm_cmpeq_pi32 (__m64 m1, __m64 m2)

(V)PCMPEQB:

__m128i _mm_cmpeq_epi8 ( __m128i a, __m128i b)

(V)PCMPEQW:

__m128i _mm_cmpeq_epi16 ( __m128i a, __m128i b)

(V)PCMPEQD:

__m128i _mm_cmpeq_epi32 ( __m128i a, __m128i b)

VPCMPEQB:

__m256i _mm256_cmpeq_epi8 ( __m256i a, __m256i b)

VPCMPEQW:

__m256i _mm256_cmpeq_epi16 ( __m256i a, __m256i b)

VPCMPEQD:

__m256i _mm256_cmpeq_epi32 ( __m256i a, __m256i b)

PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal

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INSTRUCTION SET REFERENCE, N-Z

PCMPEQQ — Compare Packed Qword Data for Equal

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

66 0F 38 29 /r

RM V/V

SSE4_1

Compare packed qwords in xmm2/m128 and

PCMPEQQ xmm1, xmm2/m128

xmm1 for equality.

VEX.NDS.128.66.0F38.WIG 29 /r

RVM V/V

AVX

Compare packed quadwords in xmm3/m128

VPCMPEQQ xmm1, xmm2, xmm3/m128

and xmm2 for equality.

VEX.NDS.256.66.0F38.WIG 29 /r

RVM V/V

AVX2

Compare packed quadwords in ymm3/m256

VPCMPEQQ ymm1, ymm2, ymm3 /m256

and ymm2 for equality.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

Description

Performs an SIMD compare for equality of the packed quadwords in the destination operand (first operand) and the

source operand (second operand). If a pair of data elements is equal, the corresponding data element in the desti-

nation is set to all 1s; otherwise, it is set to 0s.

128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The

first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination

VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The

first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register

are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation

IF (DEST[63:0] = SRC[63:0])

THEN DEST[63:0]  FFFFFFFFFFFFFFFFH;

ELSE DEST[63:0]  0; FI;

IF (DEST[127:64] = SRC[127:64])

THEN DEST[127:64]  FFFFFFFFFFFFFFFFH;

ELSE DEST[127:64]  0; FI;

VPCMPEQQ (VEX.128 encoded version)

DEST[127:0] COMPARE_QWORDS_EQUAL(SRC1,SRC2)

DEST[VLMAX-1:128]  0

VPCMPEQQ (VEX.256 encoded version)

DEST[127:0] COMPARE_QWORDS_EQUAL(SRC1[127:0],SRC2[127:0])

DEST[255:128] COMPARE_QWORDS_EQUAL(SRC1[255:128],SRC2[255:128])

Intel C/C++ Compiler Intrinsic Equivalent

(V)PCMPEQQ:

__m128i _mm_cmpeq_epi64(__m128i a, __m128i b);

VPCMPEQQ:

__m256i _mm256_cmpeq_epi64( __m256i a, __m256i b);

PCMPEQQ — Compare Packed Qword Data for Equal

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INSTRUCTION SET REFERENCE, N-Z

PCMPESTRI — Packed Compare Explicit Length Strings, Return Index

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

66 0F 3A 61 /r imm8

RMI V/V

SSE4_2

Perform a packed comparison of string data

PCMPESTRI xmm1, xmm2/m128, imm8

with explicit lengths, generating an index, and

storing the result in ECX.

VEX.128.66.0F3A.WIG 61 /r ib

RMI V/V

AVX

Perform a packed comparison of string data

VPCMPESTRI xmm1, xmm2/m128, imm8

with explicit lengths, generating an index, and

storing the result in ECX.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RMI

ModRM:reg (r)

ModRM:r/m (r)

imm8

Description

The instruction compares and processes data from two string fragments based on the encoded value in the Imm8

Control Byte (see Section 4.1, “Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMP-

ISTRM”), and generates an index stored to the count register (ECX/RCX).

Each string fragment is represented by two values. The first value is an xmm (or possibly m128 for the second

operand) which contains the data elements of the string (byte or word data). The second value is stored in an input

length register. The input length register is EAX/RAX (for xmm1) or EDX/RDX (for xmm2/m128). The length repre-

sents the number of bytes/words which are valid for the respective xmm/m128 data.

The length of each input is interpreted as being the absolute-value of the value in the length register. The absolute-

value computation saturates to 16 (for bytes) and 8 (for words), based on the value of imm8[bit3] when the value

in the length register is greater than 16 (8) or less than -16 (-8).

The comparison and aggregation operations are performed according to the encoded value of Imm8 bit fields (see

Section 4.1). The index of the first (or last, according to imm8[6]) set bit of IntRes2 (see Section 4.1.4) is returned

in ECX. If no bits are set in IntRes2, ECX is set to 16 (8).

Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant informa-

tion:

CFlag - Reset if IntRes2 is equal to zero, set otherwise

ZFlag - Set if absolute-value of EDX is < 16 (8), reset otherwise

SFlag - Set if absolute-value of EAX is < 16 (8), reset otherwise

OFlag - IntRes2[0]

AFlag - Reset

PFlag - Reset

Effective Operand Size

Operating mode/size

Operand 1

Operand 2

Length 1

Length 2

Result

16 bit

xmm

xmm/m128

EAX

EDX

ECX

32 bit

xmm

xmm/m128

EAX

EDX

ECX

64 bit

xmm

xmm/m128

EAX

EDX

ECX

64 bit + REX.W

xmm

xmm/m128

RAX

RDX

RCX

Intel C/C++ Compiler Intrinsic Equivalent For Returning Index

int

_mm_cmpestri (__m128i a, int la, __m128i b, int lb, const int mode);

PCMPESTRI — Packed Compare Explicit Length Strings, Return Index

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INSTRUCTION SET REFERENCE, N-Z

PCMPESTRM — Packed Compare Explicit Length Strings, Return Mask

Opcode/

Op/

64/32 bit CPUID

Description

Instruction

En Mode

Feature

Support Flag

66 0F 3A 60 /r imm8

RMI V/V

SSE4_2

Perform a packed comparison of string data

PCMPESTRM xmm1, xmm2/m128, imm8

with explicit lengths, generating a mask, and

storing the result in XMM0

VEX.128.66.0F3A.WIG 60 /r ib

RMI V/V

AVX

Perform a packed comparison of string data

VPCMPESTRM xmm1, xmm2/m128, imm8

with explicit lengths, generating a mask, and

storing the result in XMM0.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RMI

ModRM:reg (r)

ModRM:r/m (r)

imm8

Description

The instruction compares data from two string fragments based on the encoded value in the imm8 contol byte (see

Section 4.1, “Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM”), and gener-

ates a mask stored to XMM0.